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Message-ID: <41151f25-4622-f906-06a2-e8cd65e4b211@quicinc.com>
Date:   Wed, 16 Aug 2023 20:37:47 +0530
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Subject: Re: [PATCH v2 2/3] arm64: dts: qcom: sm8450: Add opp table support to
 PCIe
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To:     Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
CC:     <manivannan.sadhasivam@linaro.org>, <helgaas@kernel.org>,
        <linux-pci@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <quic_vbadigan@quicinc.com>,
        <quic_nitegupt@quicinc.com>, <quic_skananth@quicinc.com>,
        <quic_ramkri@quicinc.com>, <quic_parass@quicinc.com>,
        <krzysztof.kozlowski@linaro.org>, Andy Gross <agross@kernel.org>,
        "Bjorn Andersson" <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@vger.kernel.org>
References: <1692192264-18515-1-git-send-email-quic_krichai@quicinc.com>
 <1692192264-18515-3-git-send-email-quic_krichai@quicinc.com>
 <CAA8EJpoi0BkuQZef=v3JxB-axXe+jB0bEWCmsk1ZJYiaWiuevw@mail.gmail.com>
From:   Krishna Chaitanya Chundru <quic_krichai@quicinc.com>
In-Reply-To: <CAA8EJpoi0BkuQZef=v3JxB-axXe+jB0bEWCmsk1ZJYiaWiuevw@mail.gmail.com>
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On 8/16/2023 7:10 PM, Dmitry Baryshkov wrote:
> On Wed, 16 Aug 2023 at 16:25, Krishna chaitanya chundru
> <quic_krichai@quicinc.com> wrote:
>> PCIe needs to choose the appropriate performance state of RPMH power
>> domain based upon the PCIe gen speed.
>>
>> So let's add the OPP table support to specify RPMH performance states.
>>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8450.dtsi | 47 ++++++++++++++++++++++++++++++++++++
>>   1 file changed, 47 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> index 595533a..c77a683 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> @@ -1803,7 +1803,28 @@
>>                          pinctrl-names = "default";
>>                          pinctrl-0 = <&pcie0_default_state>;
>>
>> +                       operating-points-v2 = <&pcie0_opp_table>;
>> +
>>                          status = "disabled";
>> +
>> +                       pcie0_opp_table: opp-table {
>> +                               compatible = "operating-points-v2";
>> +
>> +                               opp-2500000 {
> As a random suggestion: these frequencies are calculated by the
> driver. It might be easier to use opp-level for the PCIe generation
> instead.
>
> This way this OPP entry can become:
>
> opp-1 {
>      opp-level = <1>;
>      required-opps = <&rpmhpd_opp_low_svs>;
> };

This looks good I will try to do in this approach in the next patch if 
there are no other comments.

- KC

>
>> +                                       opp-hz = /bits/ 64 <2500000>;
>> +                                       required-opps = <&rpmhpd_opp_low_svs>;
>> +                               };
>> +
>> +                               opp-5000000 {
>> +                                       opp-hz = /bits/ 64 <5000000>;
>> +                                       required-opps = <&rpmhpd_opp_low_svs>;
>> +                               };
>> +
>> +                               opp-8000000 {
>> +                                       opp-hz = /bits/ 64 <8000000>;
>> +                                       required-opps = <&rpmhpd_opp_nom>;
>> +                               };
>> +                       };
>>                  };
>>
>>                  pcie0_phy: phy@1c06000 {
>> @@ -1915,7 +1936,33 @@
>>                          pinctrl-names = "default";
>>                          pinctrl-0 = <&pcie1_default_state>;
>>
>> +                       operating-points-v2 = <&pcie1_opp_table>;
>> +
>>                          status = "disabled";
>> +
>> +                       pcie1_opp_table: opp-table {
>> +                               compatible = "operating-points-v2";
>> +
>> +                               opp-2500000 {
>> +                                       opp-hz = /bits/ 64 <2500000>;
>> +                                       required-opps = <&rpmhpd_opp_low_svs>;
>> +                               };
>> +
>> +                               opp-5000000 {
>> +                                       opp-hz = /bits/ 64 <5000000>;
>> +                                       required-opps = <&rpmhpd_opp_low_svs>;
>> +                               };
>> +
>> +                               opp-8000000 {
>> +                                       opp-hz = /bits/ 64 <8000000>;
>> +                                       required-opps = <&rpmhpd_opp_low_svs>;
>> +                               };
>> +
>> +                               opp-16000000 {
>> +                                       opp-hz = /bits/ 64 <16000000>;
>> +                                       required-opps = <&rpmhpd_opp_nom>;
>> +                               };
>> +                       };
>>                  };
>>
>>                  pcie1_phy: phy@1c0f000 {
>> --
>> 2.7.4
>>
>