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Message-ID: <c9ac528a-e1c2-0f64-c50e-30fc1eb6e9ac@starfivetech.com>
Date:   Wed, 23 Aug 2023 10:45:16 +0800
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Subject: Re: [PATCH v2 4/5] riscv: dts: starfive: pinfunc: Fix the pins name
 of I2STX1
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To:     Xingyu Wu <xingyu.wu@starfivetech.com>,
        Liam Girdwood <lgirdwood@gmail.com>,
        Mark Brown <broonie@kernel.org>,
        Claudiu Beznea <Claudiu.Beznea@microchip.com>,
        Jaroslav Kysela <perex@perex.cz>,
        "Takashi Iwai" <tiwai@suse.com>,
        Maxim Kochetkov <fido_max@inbox.ru>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor.dooley@microchip.com>,
        Emil Renner Berthing <emil.renner.berthing@canonical.com>
CC:     Jose Abreu <joabreu@synopsys.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <alsa-devel@alsa-project.org>, <linux-riscv@lists.infradead.org>
References: <20230821144151.207339-1-xingyu.wu@starfivetech.com>
 <20230821144151.207339-5-xingyu.wu@starfivetech.com>
From:   Walker Chen <walker.chen@starfivetech.com>
In-Reply-To: <20230821144151.207339-5-xingyu.wu@starfivetech.com>
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On 2023/8/21 22:41, Xingyu Wu wrote:
> These pins are actually I2STX1 clock input, not I2STX0,
> so their names should be changed.
> 
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---
>  arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h b/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
> index fb0139b56723..256de17f5261 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
> +++ b/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
> @@ -240,8 +240,8 @@
>  #define GPI_SYS_MCLK_EXT			30
>  #define GPI_SYS_I2SRX_BCLK			31
>  #define GPI_SYS_I2SRX_LRCK			32
> -#define GPI_SYS_I2STX0_BCLK			33
> -#define GPI_SYS_I2STX0_LRCK			34
> +#define GPI_SYS_I2STX1_BCLK			33
> +#define GPI_SYS_I2STX1_LRCK			34
>  #define GPI_SYS_TDM_CLK				35
>  #define GPI_SYS_TDM_RXD				36
>  #define GPI_SYS_TDM_SYNC			37

Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Thanks!