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From:   Guo Ren <guoren@kernel.org>
Date:   Sun, 27 Aug 2023 06:23:33 -0400
Message-ID: <CAJF2gTSC18XVsH+X7sn4RC_j-pWNmO+4oWz0OWtQp=vKSPC2tQ@mail.gmail.com>
Subject: Re: [PATCH] riscv: mm: update T-Head memory type definitions
To:     Jisheng Zhang <jszhang@kernel.org>
Cc:     Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
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On Sun, Aug 27, 2023 at 5:18=E2=80=AFAM Jisheng Zhang <jszhang@kernel.org> =
wrote:
>
> Update T-Head memory type definitions according to C910 doc [1]
> For NC and IO, SH property isn't configurable, hardcoded as SH,
> so set SH for NOCACHE and IO.
>
> And also set bit[61](Bufferable) for NOCACHE according to the
> table 6.1 in the doc [1].
>
> Link: https://github.com/T-head-Semi/openc910 [1]
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  arch/riscv/include/asm/pgtable-64.h | 14 +++++++++-----
>  1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm=
/pgtable-64.h
> index 7a5097202e15..9a2c780a11e9 100644
> --- a/arch/riscv/include/asm/pgtable-64.h
> +++ b/arch/riscv/include/asm/pgtable-64.h
> @@ -126,14 +126,18 @@ enum napot_cont_order {
>
>  /*
>   * [63:59] T-Head Memory Type definitions:
> - *
> - * 00000 - NC   Weakly-ordered, Non-cacheable, Non-bufferable, Non-share=
able, Non-trustable
> + * bit[63] SO - Strong Order
> + * bit[62] C - Cacheable
> + * bit[61] B - Bufferable
> + * bit[60] SH - Shareable
> + * bit[59] Sec - Trustable
> + * 00110 - NC   Weakly-ordered, Non-cacheable, Bufferable, Shareable, No=
n-trustable
>   * 01110 - PMA  Weakly-ordered, Cacheable, Bufferable, Shareable, Non-tr=
ustable
> - * 10000 - IO   Strongly-ordered, Non-cacheable, Non-bufferable, Non-sha=
reable, Non-trustable
> + * 10010 - IO   Strongly-ordered, Non-cacheable, Non-bufferable, Shareab=
le, Non-trustable
>   */
>  #define _PAGE_PMA_THEAD                ((1UL << 62) | (1UL << 61) | (1UL=
 << 60))
> -#define _PAGE_NOCACHE_THEAD    0UL
> -#define _PAGE_IO_THEAD         (1UL << 63)
> +#define _PAGE_NOCACHE_THEAD    ((1UL < 61) | (1UL << 60))
> +#define _PAGE_IO_THEAD         ((1UL << 63) | (1UL << 60))
Yes, SH does not affect D1, but let's keep th1520 & d1 & sg2042 with
the same definitions.

Reviewed-by: Guo Ren <guoren@kernel.org>

>  #define _PAGE_MTMASK_THEAD     (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL =
<< 59))
>
>  static inline u64 riscv_page_mtmask(void)
> --
> 2.40.1
>


--=20
Best Regards
 Guo Ren