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Message-ID: <503bbb09-2886-9dbb-808a-65422bab712c@starfivetech.com>
Date:   Tue, 29 Aug 2023 17:41:21 +0800
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Subject: Re: [RFC v4 4/4] riscv: dts: starfive: jh7100: Add PWM node and pins
 configuration
To:     Emil Renner Berthing <emil.renner.berthing@canonical.com>
CC:     <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-riscv@lists.infradead.org>, <linux-pwm@vger.kernel.org>,
        "Emil Renner Berthing" <kernel@esmil.dk>,
        Rob Herring <robh+dt@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Thierry Reding <thierry.reding@gmail.com>,
        =?UTF-8?Q?Uwe_Kleine-K=c3=b6nig?= <u.kleine-koenig@pengutronix.de>,
        "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        "Palmer Dabbelt" <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Hal Feng <hal.feng@starfivetech.com>
References: <20230825081328.204442-1-william.qiu@starfivetech.com>
 <20230825081328.204442-5-william.qiu@starfivetech.com>
 <CAJM55Z-Ab1DAQyQC9TRFFBidus6wCRns9RQjx-iyYyNK1e-e6A@mail.gmail.com>
Content-Language: en-US
From:   William Qiu <william.qiu@starfivetech.com>
In-Reply-To: <CAJM55Z-Ab1DAQyQC9TRFFBidus6wCRns9RQjx-iyYyNK1e-e6A@mail.gmail.com>
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On 2023/8/29 17:38, Emil Renner Berthing wrote:
> On Fri, 25 Aug 2023 at 10:16, William Qiu <william.qiu@starfivetech.com> wrote:
>> Add StarFive JH7100 PWM controller node and add PWM pins configuration
>> on VisionFive 2 board.
> 
> Hi William,
> 
> This is the VisionFive V1 board right?
> 
> /Emil
> 
Hi Emil,

Yes， it's VisionFive V1, I wrote it wrong.

B.R.
William
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>>  .../boot/dts/starfive/jh7100-common.dtsi      | 24 +++++++++++++++++++
>>  arch/riscv/boot/dts/starfive/jh7100.dtsi      |  9 +++++++
>>  2 files changed, 33 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
>> index b93ce351a90f..746867b882b0 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
>> @@ -84,6 +84,24 @@ GPO_I2C2_PAD_SDA_OEN,
>>                 };
>>         };
>>
>> +       pwm_pins: pwm-0 {
>> +               pwm-pins {
>> +                       pinmux = <GPIOMUX(7,
>> +                                 GPO_PWM_PAD_OUT_BIT0,
>> +                                 GPO_PWM_PAD_OE_N_BIT0,
>> +                                 GPI_NONE)>,
>> +                                <GPIOMUX(5,
>> +                                 GPO_PWM_PAD_OUT_BIT1,
>> +                                 GPO_PWM_PAD_OE_N_BIT1,
>> +                                 GPI_NONE)>;
>> +                       bias-disable;
>> +                       drive-strength = <35>;
>> +                       input-disable;
>> +                       input-schmitt-disable;
>> +                       slew-rate = <0>;
>> +               };
>> +       };
>> +
>>         uart3_pins: uart3-0 {
>>                 rx-pins {
>>                         pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
>> @@ -154,6 +172,12 @@ &osc_aud {
>>         clock-frequency = <27000000>;
>>  };
>>
>> +&ptc {
>> +       pinctrl-names = "default";
>> +       pinctrl-0 = <&pwm_pins>;
>> +       status = "okay";
>> +};
>> +
>>  &uart3 {
>>         pinctrl-names = "default";
>>         pinctrl-0 = <&uart3_pins>;
>> diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
>> index 4218621ea3b9..7f5bb19e636e 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
>> @@ -248,5 +248,14 @@ watchdog@12480000 {
>>                         resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
>>                                  <&rstgen JH7100_RSTN_WDT>;
>>                 };
>> +
>> +               ptc: pwm@12490000 {
>> +                       compatible = "starfive,jh7100-pwm";
>> +                       reg = <0x0 0x12490000 0x0 0x10000>;
>> +                       clocks = <&clkgen JH7100_CLK_PWM_APB>;
>> +                       resets = <&rstgen JH7100_RSTN_PWM_APB>;
>> +                       #pwm-cells = <3>;
>> +                       status = "disabled";
>> +               };
>>         };
>>  };
>> --
>> 2.34.1
>>
>>
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>> linux-riscv@lists.infradead.org
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