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From:   Anastasia Belova <abelova@astralinux.ru>
To:     Michael Turquette <mturquette@baylibre.com>
Cc:     Anastasia Belova <abelova@astralinux.ru>,
        Stephen Boyd <sboyd@kernel.org>,
        Mike Looijmans <mike.looijmans@topic.nl>,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        lvc-project@linuxtesting.org
Subject: [PATCH] clk: cdce925: change condition in cdce925_clk_round_rate
Date:   Fri,  1 Sep 2023 16:03:59 +0300
Message-Id: <20230901130359.20561-1-abelova@astralinux.ru>
MIME-Version: 1.0
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Precedence: bulk

To avoid division by zero add check if
divider is zero.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Fixes: 19fbbbbcd3a3 ("Add TI CDCE925 I2C controlled clock synthesizer dri=
ver")
Signed-off-by: Anastasia Belova <abelova@astralinux.ru>
---
 drivers/clk/clk-cdce925.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-cdce925.c b/drivers/clk/clk-cdce925.c
index 96ac90364847..d903cdc3ad7d 100644
--- a/drivers/clk/clk-cdce925.c
+++ b/drivers/clk/clk-cdce925.c
@@ -441,7 +441,7 @@ static long cdce925_clk_round_rate(struct clk_hw *hw,=
 unsigned long rate,
 	unsigned long l_parent_rate =3D *parent_rate;
 	u16 divider =3D cdce925_calc_divider(rate, l_parent_rate);
=20
-	if (l_parent_rate / divider !=3D rate) {
+	if (divider && l_parent_rate / divider !=3D rate) {
 		l_parent_rate =3D cdce925_clk_best_parent_rate(hw, rate);
 		divider =3D cdce925_calc_divider(rate, l_parent_rate);
 		*parent_rate =3D l_parent_rate;
--=20
2.30.2