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From:   Guo Ren <guoren@kernel.org>
Date:   Tue, 12 Sep 2023 22:48:27 +0800
Message-ID: <CAJF2gTTSLabt4WFgkDoHWpTuv=KTcQTK7gfNVhS-d7yHOe2fRw@mail.gmail.com>
Subject: Re: [PATCH v2] riscv: dts: thead: set dma-noncoherent to soc bus
To:     Jisheng Zhang <jszhang@kernel.org>
Cc:     Fu Wei <wefu@redhat.com>, Conor Dooley <conor@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, Drew Fustini <dfustini@baylibre.com>
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On Tue, Sep 12, 2023 at 3:34=E2=80=AFPM Jisheng Zhang <jszhang@kernel.org> =
wrote:
>
> riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
> dma coherent, so set dma-noncoherent to reflect this fact.
>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> Tested-by: Drew Fustini <dfustini@baylibre.com>
> ---
>
> Since v1:
>  - rebase on v6.6-rc1
>  - collect Tested-by tag
>
>  arch/riscv/boot/dts/thead/th1520.dtsi | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/=
thead/th1520.dtsi
> index ce708183b6f6..ff364709a6df 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -139,6 +139,7 @@ soc {
>                 interrupt-parent =3D <&plic>;
>                 #address-cells =3D <2>;
>                 #size-cells =3D <2>;
> +               dma-noncoherent;
Reviewed-by: Guo Ren <guoren@kernel.org>

>                 ranges;
>
>                 plic: interrupt-controller@ffd8000000 {
> --
> 2.40.1
>


--=20
Best Regards
 Guo Ren