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Subject: Re: [PATCH v3 4/5] clk: twl: add clock driver for TWL6032
From:   Stephen Boyd <sboyd@kernel.org>
To:     andreas@kemnade.info, bcousson@baylibre.com, conor+dt@kernel.org,
        devicetree@vger.kernel.org, dmitry.torokhov@gmail.com,
        krzysztof.kozlowski+dt@linaro.org, lee@kernel.org,
        linux-clk@vger.kernel.org, linux-input@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org,
        mturquette@baylibre.com, robh+dt@kernel.org, tony@atomide.com
Date:   Tue, 12 Sep 2023 11:04:02 -0700
User-Agent: alot/0.10
Precedence: bulk

Quoting Andreas Kemnade (2023-09-11 15:13:45)
> diff --git a/drivers/clk/clk-twl.c b/drivers/clk/clk-twl.c
> new file mode 100644
> index 0000000000000..09006e53a32ec
> --- /dev/null
> +++ b/drivers/clk/clk-twl.c
> @@ -0,0 +1,197 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Clock driver for twl device.
> + *
> + * inspired by the driver for the Palmas device
> + */
> +
> +#include <linux/clk.h>

Please drop this include unless it is used.

> +#include <linux/clk-provider.h>
> +#include <linux/mfd/twl.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#define VREG_STATE              2
> +#define TWL6030_CFG_STATE_OFF   0x00
> +#define TWL6030_CFG_STATE_ON    0x01
> +#define TWL6030_CFG_STATE_MASK  0x03
> +
> +struct twl_clock_info {
> +       struct device *dev;
> +       u8 base;
> +       struct clk_hw hw;
> +};
[...]
> +
> +static int twl_clks_probe(struct platform_device *pdev)
> +{
> +       struct clk_hw_onecell_data *clk_data;
> +       const struct twl_clks_data *hw_data;
> +
> +       struct twl_clock_info *cinfo;
> +       int ret;
> +       int i;
> +       int count;
> +
> +       hw_data =3D twl6032_clks;
> +       for (count =3D 0; hw_data[count].init.name; count++)
> +               ;
> +
> +       clk_data =3D devm_kzalloc(&pdev->dev,
> +                               struct_size(clk_data, hws, count),
> +                               GFP_KERNEL);
> +       if (!clk_data)
> +               return -ENOMEM;
> +
> +       clk_data->num =3D count;
> +       cinfo =3D devm_kcalloc(&pdev->dev, count, sizeof(*cinfo), GFP_KER=
NEL);
> +       if (!cinfo)
> +               return -ENOMEM;
> +
> +       for (i =3D 0; i < count; i++) {
> +               cinfo[i].base =3D hw_data[i].base;
> +               cinfo[i].dev =3D &pdev->dev;
> +               cinfo[i].hw.init =3D &hw_data[i].init;
> +               ret =3D devm_clk_hw_register(&pdev->dev, &cinfo[i].hw);
> +               if (ret) {
> +                       dev_err(&pdev->dev, "Fail to register clock %s, %=
d\n",

Use dev_err_probe()

> +                               hw_data[i].init.name, ret);
> +                       return ret;
> +               }
> +               clk_data->hws[i] =3D &cinfo[i].hw;
> +       }
> +
> +       ret =3D devm_of_clk_add_hw_provider(&pdev->dev,
> +                                         of_clk_hw_onecell_get, clk_data=
);
> +       if (ret < 0)
> +               dev_err(&pdev->dev, "Fail to add clock driver, %d\n", ret=
);

Use dev_err_probe()

> +
> +       return ret;