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Message-ID: <7b73c07a-c229-9d95-7069-7d80df465ffb@intel.com>
Date:   Tue, 12 Sep 2023 09:13:45 -0700
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Subject: Re: [PATCH 1/3] x86/resctrl: Enable non-contiguous bits in Intel CAT
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To:     =?UTF-8?Q?Maciej_Wiecz=c3=b3r-Retman?= 
        <maciej.wieczor-retman@intel.com>
CC:     Fenghua Yu <fenghua.yu@intel.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        Dave Hansen <dave.hansen@linux.intel.com>, <x86@kernel.org>,
        "H. Peter Anvin" <hpa@zytor.com>, <linux-kernel@vger.kernel.org>
References: <cover.1693557919.git.maciej.wieczor-retman@intel.com>
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 <ob4e7sb4pfitjn7arlt7f6be3hvdoyp5yecb4o5ub3i36u2qhv@4s6vzu5nk342>
From:   Reinette Chatre <reinette.chatre@intel.com>
In-Reply-To: <ob4e7sb4pfitjn7arlt7f6be3hvdoyp5yecb4o5ub3i36u2qhv@4s6vzu5nk342>
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Hi Maciej,

On 9/11/2023 11:53 PM, Maciej Wieczór-Retman wrote:
> On 2023-09-11 at 13:05:16 -0700, Reinette Chatre wrote:
>> Hi Maciej,
>>> diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
>>> index b44c487727d4..782e2700290b 100644
>>> --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
>>> +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c
>>> @@ -87,10 +87,13 @@ int parse_bw(struct rdt_parse_data *data, struct resctrl_schema *s,
>>>  
>>>  /*
>>>   * Check whether a cache bit mask is valid.
>>> - * For Intel the SDM says:
>>> - *	Please note that all (and only) contiguous '1' combinations
>>> - *	are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.).
>>> - * Additionally Haswell requires at least two bits set.
>>> + * On Intel CPUs, non-contiguous 1s value support is indicated by CPUID:
>>> + *   - CPUID.0x10.1:ECX[3]: L3 non-contiguous 1s value supported if 1
>>> + *   - CPUID.0x10.2:ECX[3]: L2 non-contiguous 1s value supported if 1
>>> + *
>>> + * Additionally Haswell requires at least two bits set. Since it does not
>>> + * have CPUID enumeration support for Cache allocation the non-contiguous 1s
>>> + * value support is disabled.
>>
>> The second sentence can be misinterpreted. non-contiguous 1s value support is
>> disabled on Haswell because Haswell does not support non-contiguous 1s value,
>> not because it does not have CPUID enumeration for RDT.
> 
> Would phrasing it like this:
> 
> + * Additionally Haswell requires at least two bits set. Since it does not
> + * allow the non-contiguous 1s for cache allocation the support is
> + * hardcoded to disabled.
> 
> be more sensible?
> 

I think the above would be sensible as a comment of cache_alloc_hsw_probe()
where the support is hardcoded but here the comment is just used to summarize
what the hardware supports.
Maybe just something like:
	Haswell does not support a non-contiguous 1s value and additionally
	requires at least two bits set.

Reinette