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Date:   Wed, 13 Sep 2023 14:11:36 +0100
From:   Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To:     Jinhui Guo <guojinhui.liam@bytedance.com>,
        <linux-kernel@vger.kernel.org>
CC:     <catalin.marinas@arm.com>, <linux-arm-kernel@lists.infradead.org>,
        <lizefan.x@bytedance.com>, <robin.murphy@arm.com>,
        <will@kernel.org>
Subject: Re: [PATCH] arm64: cpufeature: Expose the real mpidr value to EL0
Message-ID: <20230913141136.00006a47@Huawei.com>
In-Reply-To: <20230913105133.2902-1-guojinhui.liam@bytedance.com>
References: <20230912115116.000049b0@Huawei.com>
        <20230913105133.2902-1-guojinhui.liam@bytedance.com>
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On Wed, 13 Sep 2023 18:51:33 +0800
Jinhui Guo <guojinhui.liam@bytedance.com> wrote:

> > As a follow up question, is there some information that is missing from
> > current topology description?  (there is lots missing but I'm curious
> > as to what might matter for your use case!)  
> 
> We want to know the infomation about dies to advoid memroy accessing
> across dies (some settings like 2 numa per die).

The NUMA access characteristics should give you the info you want - it's
the variation in latency and bandwidth between dies that matters, not that
they are dies.  If you got really bad access characteristics across a die
that info would be equally useful.

I think it is not that this is a die that matters, but rather that there
are groups of Numa nodes with relatively small differences in access
characteristics, then others with much larger variation (and I assume
a layer above that which is inter socket which is even worse).

The info is in HMAT, but the kernel presentation of HMAT is rather limited
currently - so you may want to look at extending what is visible in sysfs
from that table.

Thanks,

Jonathan

> 
> thanks,
> 
> Jinhui Guo
>