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 <20230911131224.61924-5-alexghiti@rivosinc.com> <CAHVXubiVH=q9pnTLQyjS3X3W-hvuA=ZMM2D2xYPFkGjFnAgbWg@mail.gmail.com>
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From:   "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date:   Wed, 13 Sep 2023 09:23:08 +0100
Message-ID: <CA+V-a8tYzee-cX8rMiQ66ENWb+rLLFHmkOdovft0L-8ASQ3eog@mail.gmail.com>
Subject: Re: [PATCH v4 4/4] riscv: Improve flush_tlb_kernel_range()
To:     Alexandre Ghiti <alexghiti@rivosinc.com>
Cc:     Will Deacon <will@kernel.org>,
        "Aneesh Kumar K . V" <aneesh.kumar@linux.ibm.com>,
        Andrew Morton <akpm@linux-foundation.org>,
        Nick Piggin <npiggin@gmail.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Mayuresh Chitale <mchitale@ventanamicro.com>,
        Vincent Chen <vincent.chen@sifive.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>, linux-arch@vger.kernel.org,
        linux-mm@kvack.org, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org, Samuel Holland <samuel@sholland.org>,
        Andrew Jones <ajones@ventanamicro.com>
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Hi Alexandre,

On Wed, Sep 13, 2023 at 9:04=E2=80=AFAM Alexandre Ghiti <alexghiti@rivosinc=
.com> wrote:
>
> @Lad, Prabhakar Any chance you give a try to this new patchset? So
> that we make sure Samuel found your issue :)
>
I have given the patches a try and not seen the module load failures
as seen previously. I have some rigorous tests which test the complete
platform. I'm just waiting for it to complete before I give Tested by.

Cheers,
Prabhakar

> On Mon, Sep 11, 2023 at 3:16=E2=80=AFPM Alexandre Ghiti <alexghiti@rivosi=
nc.com> wrote:
> >
> > This function used to simply flush the whole tlb of all harts, be more
> > subtile and try to only flush the range.
> >
> > The problem is that we can only use PAGE_SIZE as stride since we don't =
know
> > the size of the underlying mapping and then this function will be impro=
ved
> > only if the size of the region to flush is < threshold * PAGE_SIZE.
> >
> > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> > ---
> >  arch/riscv/include/asm/tlbflush.h | 11 ++++++-----
> >  arch/riscv/mm/tlbflush.c          | 33 ++++++++++++++++++++++---------
> >  2 files changed, 30 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm=
/tlbflush.h
> > index 170a49c531c6..8f3418c5f172 100644
> > --- a/arch/riscv/include/asm/tlbflush.h
> > +++ b/arch/riscv/include/asm/tlbflush.h
> > @@ -40,6 +40,7 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigne=
d long start,
> >  void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr);
> >  void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
> >                      unsigned long end);
> > +void flush_tlb_kernel_range(unsigned long start, unsigned long end);
> >  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> >  #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
> >  void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long sta=
rt,
> > @@ -56,15 +57,15 @@ static inline void flush_tlb_range(struct vm_area_s=
truct *vma,
> >         local_flush_tlb_all();
> >  }
> >
> > -#define flush_tlb_mm(mm) flush_tlb_all()
> > -#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all()
> > -#endif /* !CONFIG_SMP || !CONFIG_MMU */
> > -
> >  /* Flush a range of kernel pages */
> >  static inline void flush_tlb_kernel_range(unsigned long start,
> >         unsigned long end)
> >  {
> > -       flush_tlb_all();
> > +       local_flush_tlb_all();
> >  }
> >
> > +#define flush_tlb_mm(mm) flush_tlb_all()
> > +#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all()
> > +#endif /* !CONFIG_SMP || !CONFIG_MMU */
> > +
> >  #endif /* _ASM_RISCV_TLBFLUSH_H */
> > diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> > index 2c1136d73411..28cd8539b575 100644
> > --- a/arch/riscv/mm/tlbflush.c
> > +++ b/arch/riscv/mm/tlbflush.c
> > @@ -97,19 +97,27 @@ static void __flush_tlb_range(struct mm_struct *mm,=
 unsigned long start,
> >                               unsigned long size, unsigned long stride)
> >  {
> >         struct flush_tlb_range_data ftd;
> > -       struct cpumask *cmask =3D mm_cpumask(mm);
> > +       struct cpumask *cmask, full_cmask;
> >         unsigned long asid =3D FLUSH_TLB_NO_ASID;
> > -       unsigned int cpuid;
> >         bool broadcast;
> >
> > -       if (cpumask_empty(cmask))
> > -               return;
> > +       if (mm) {
> > +               unsigned int cpuid;
> > +
> > +               cmask =3D mm_cpumask(mm);
> > +               if (cpumask_empty(cmask))
> > +                       return;
> >
> > -       cpuid =3D get_cpu();
> > -       /* check if the tlbflush needs to be sent to other CPUs */
> > -       broadcast =3D cpumask_any_but(cmask, cpuid) < nr_cpu_ids;
> > +               cpuid =3D get_cpu();
> > +               /* check if the tlbflush needs to be sent to other CPUs=
 */
> > +               broadcast =3D cpumask_any_but(cmask, cpuid) < nr_cpu_id=
s;
> > +       } else {
> > +               cpumask_setall(&full_cmask);
> > +               cmask =3D &full_cmask;
> > +               broadcast =3D true;
> > +       }
> >
> > -       if (static_branch_unlikely(&use_asid_allocator))
> > +       if (static_branch_unlikely(&use_asid_allocator) && mm)
> >                 asid =3D atomic_long_read(&mm->context.id) & asid_mask;
> >
> >         if (broadcast) {
> > @@ -128,7 +136,8 @@ static void __flush_tlb_range(struct mm_struct *mm,=
 unsigned long start,
> >                 local_flush_tlb_range_asid(start, size, stride, asid);
> >         }
> >
> > -       put_cpu();
> > +       if (mm)
> > +               put_cpu();
> >  }
> >
> >  void flush_tlb_mm(struct mm_struct *mm)
> > @@ -189,6 +198,12 @@ void flush_tlb_range(struct vm_area_struct *vma, u=
nsigned long start,
> >
> >         __flush_tlb_range(vma->vm_mm, start, end - start, stride_size);
> >  }
> > +
> > +void flush_tlb_kernel_range(unsigned long start, unsigned long end)
> > +{
> > +       __flush_tlb_range(NULL, start, end - start, PAGE_SIZE);
> > +}
> > +
> >  #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> >  void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long sta=
rt,
> >                         unsigned long end)
> > --
> > 2.39.2
> >