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From:   Ian Rogers <irogers@google.com>
Date:   Wed, 13 Sep 2023 16:24:01 -0700
Message-ID: <CAP-5=fU=8RwHsd=nP6evT2oxCeOvXF4dfNF9MhBVk3y2WvH3MQ@mail.gmail.com>
Subject: Re: [PATCH] perf annotate: Add more x86 mov instruction cases
To:     Namhyung Kim <namhyung@kernel.org>
Cc:     David Laight <David.Laight@aculab.com>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        Jiri Olsa <jolsa@kernel.org>,
        Adrian Hunter <adrian.hunter@intel.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@kernel.org>,
        LKML <linux-kernel@vger.kernel.org>,
        "linux-perf-users@vger.kernel.org" <linux-perf-users@vger.kernel.org>
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On Wed, Sep 13, 2023 at 2:14=E2=80=AFPM Namhyung Kim <namhyung@kernel.org> =
wrote:
>
> On Mon, Sep 11, 2023 at 1:12=E2=80=AFAM David Laight <David.Laight@aculab=
.com> wrote:
> >
> > From: Namhyung Kim
> > > Sent: 09 September 2023 00:56
> > >
> > > Hi Ian,
> > >
> > > On Thu, Sep 7, 2023 at 11:24=E2=80=AFPM Ian Rogers <irogers@google.co=
m> wrote:
> > > >
> > > > On Thu, Sep 7, 2023 at 10:22=E2=80=AFPM Namhyung Kim <namhyung@kern=
el.org> wrote:
> > > > >
> > > > > Instructions with sign- and zero- extention like movsbl and movzw=
q were
> > > > > not handled properly.  As it can check different size suffix (-b,=
 -w, -l
> > > > > or -q) we can omit that and add the common parts even though some
> > > > > combinations are not possible.
> > > > >
> > > > > Signed-off-by: Namhyung Kim <namhyung@kernel.org>
> > > > > ---
> > > > >  tools/perf/arch/x86/annotate/instructions.c | 9 ++++++---
> > > > >  1 file changed, 6 insertions(+), 3 deletions(-)
> > > > >
> > > > > diff --git a/tools/perf/arch/x86/annotate/instructions.c
> > > b/tools/perf/arch/x86/annotate/instructions.c
> > > > > index 5f4ac4fc7fcf..5cdf457f5cbe 100644
> > > > > --- a/tools/perf/arch/x86/annotate/instructions.c
> > > > > +++ b/tools/perf/arch/x86/annotate/instructions.c
> > > > > @@ -74,12 +74,15 @@ static struct ins x86__instructions[] =3D {
> > > > >         { .name =3D "movdqa",     .ops =3D &mov_ops,  },
> > > > >         { .name =3D "movdqu",     .ops =3D &mov_ops,  },
> > > > >         { .name =3D "movsd",      .ops =3D &mov_ops,  },
> > > > > -       { .name =3D "movslq",     .ops =3D &mov_ops,  },
> > > > >         { .name =3D "movss",      .ops =3D &mov_ops,  },
> > > > > +       { .name =3D "movsb",      .ops =3D &mov_ops,  },
> > > > > +       { .name =3D "movsw",      .ops =3D &mov_ops,  },
> > > > > +       { .name =3D "movsl",      .ops =3D &mov_ops,  },
> > > >
> > > > In Intel's manual some of these names are "Move Data From String to
> > > > String" operations, movsb and movsw in particular. These instructio=
ns
> > > > can be used to make simple memcpy loops. Could it be the past omiss=
ion
> > > > was deliberate due to the different way the addressing works in the
> > > > instructions?
> > >
> > > I don't know but in terms of instruction parsing, they are the same
> > > "MOVE" with two operands.  I'm not aware of anything in perf with
> > > the operands of these instructions.  So I guess it'd be fine to add
> > > these instructions even if they have different underlying behaviors.
> >
> > I'm pretty sure that 'rep movs[bwlq]' (aka while (cx--) *di++ =3D *si++=
)
> > is likely to be missing the memory argument parameters.
> > There is also 'fun and games' with one variant - iirc 'rep movsd'
> > what has been used for 64bit, but got hijacked by one of the SIMD sets.
>
> It seems perf annotate don't process the rep prefix yet.
> So I think there should be no functional change now.

Reading the code, I also think it should be okay. Doing:
```
$ objdump -d /usr/lib/x86_64-linux-gnu/libc.so.6 |grep rep
   2650a:       f3 ab                   rep stos %eax,%es:(%rdi)
   33b76:       f3 48 a5                rep movsq %ds:(%rsi),%es:(%rdi)
...
```
The mov parsing logic doesn't appear to care about src and dest, and
the formatting above matches other mov cases.

Reviewed-by: Ian Rogers <irogers@google.com>

Thanks,
Ian

> Thanks,
> Namhyung