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Thu, 14 Sep 2023 07:33:48 +0000 Message-ID: <97e59c09-30c8-038a-a6f9-3d862a0d3ede@intel.com> Date: Thu, 14 Sep 2023 15:33:10 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Firefox/102.0 Thunderbird/102.13.0 Subject: Re: [syzbot] [mm?] BUG: Bad page map (7) Content-Language: en-US To: Matthew Wilcox , Dave Hansen CC: syzbot , , , , References: <000000000000d099fa0604f03351@google.com> <0465d13d-83b6-163d-438d-065d03e9ba76@intel.com> <092a9bb2-727e-5849-fa4f-18535b998efc@intel.com> From: Yin Fengwei In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SI1PR02CA0001.apcprd02.prod.outlook.com (2603:1096:4:1f7::15) To CO1PR11MB4820.namprd11.prod.outlook.com (2603:10b6:303:6f::8) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PR11MB4820:EE_|DS0PR11MB7970:EE_ X-MS-Office365-Filtering-Correlation-Id: c589260f-b7a8-4389-7011-08dbb4f4ef59 X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Thu, 14 Sep 2023 00:34:41 -0700 (PDT) X-Spam-Status: No, score=-2.3 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Hi Matthew, On 9/12/23 12:59, Matthew Wilcox wrote: > On Mon, Sep 11, 2023 at 01:22:51PM -0700, Dave Hansen wrote: >> On 9/11/23 12:12, Matthew Wilcox wrote: >>> On Mon, Sep 11, 2023 at 09:55:37AM -0700, Dave Hansen wrote: >>>> On 9/11/23 09:44, Matthew Wilcox wrote: >>>>> After fixing your two typos, this assembles to 176 bytes more code than >>>>> my version. Not sure that's great. >>>> Maybe I'm a fool, but 176 bytes of text bloat isn't scaring me off too >>>> much. I'd much rather have that than another window into x86 goofiness >>>> to maintain. >>>> >>>> Does that 176 bytes translate into meaningful performance, or is it just >>>> a bunch of register bit twiddling that the CPU will sail through? >>> I'm ... not sure how to tell. It's 1120 bytes vs 944 bytes and crawling >>> through that much x86 assembly isn't my idea of a great time. I can >>> send you objdump -dr for all three options if you like? Maybe there's >>> a quick way to compare them that I've never known about. >> >> Working patches would be great if you're got 'em handy, plus your >> .config and generally what compiler you're on. > > gcc (Debian 13.2.0-2) 13.2.0 > > I don't think there's anything particularly strange about my .config > > If you compile this patch as-is, you'll get your preferred code. > Remove the #define DH and you get mine. > > I would say that 176 bytes is 3 cachelines of I$, which isn't free, > even if all the insns in it can be executed while the CPU is waiting > for cache misses. This ought to be a pretty tight loop anyway; we're > just filling in adjacent PTEs. There may not be many spare cycles > for "free" uops to execute. > > diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h > index d6ad98ca1288..c9781b8b14af 100644 > --- a/arch/x86/include/asm/pgtable.h > +++ b/arch/x86/include/asm/pgtable.h > @@ -955,6 +955,14 @@ static inline int pte_same(pte_t a, pte_t b) > return a.pte == b.pte; > } > > +static inline pte_t pte_next(pte_t pte) > +{ > + if (__pte_needs_invert(pte_val(pte))) > + return __pte(pte_val(pte) - (1UL << PFN_PTE_SHIFT)); > + return __pte(pte_val(pte) + (1UL << PFN_PTE_SHIFT)); > +} > +#define pte_next pte_next > + > static inline int pte_present(pte_t a) > { > return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE); > diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h > index 1fba072b3dac..25333cf3c865 100644 > --- a/include/linux/pgtable.h > +++ b/include/linux/pgtable.h > @@ -205,6 +205,10 @@ static inline int pmd_young(pmd_t pmd) > #define arch_flush_lazy_mmu_mode() do {} while (0) > #endif > > +#ifndef pte_next > +#define pte_next(pte) ((pte) + (1UL << PFN_PTE_SHIFT)) > +#endif > + > #ifndef set_ptes > /** > * set_ptes - Map consecutive pages to a contiguous range of addresses. > @@ -223,6 +227,11 @@ static inline int pmd_young(pmd_t pmd) > static inline void set_ptes(struct mm_struct *mm, unsigned long addr, > pte_t *ptep, pte_t pte, unsigned int nr) > { > +#define DH > +#ifdef DH > + pgprot_t prot = pte_pgprot(pte); > + unsigned long pfn = pte_pfn(pte); > +#endif > page_table_check_ptes_set(mm, ptep, pte, nr); > > arch_enter_lazy_mmu_mode(); > @@ -231,7 +240,12 @@ static inline void set_ptes(struct mm_struct *mm, unsigned long addr, > if (--nr == 0) > break; > ptep++; > - pte = __pte(pte_val(pte) + (1UL << PFN_PTE_SHIFT)); > +#ifdef DH > + pfn++; > + pte = pfn_pte(pfn, prot); > +#else > + pte = pte_next(pte); > +#endif > } > arch_leave_lazy_mmu_mode(); > } I checked the commit message of 6b28baca9b1f0d4a42b865da7a05b1c81424bd5c: The invert is done by pte/pmd_modify and pfn/pmd/pud_pte for PROTNONE and pte/pmd/pud_pfn undo it. This assume that no code path touches the PFN part of a PTE directly without using these primitives. So maybe we should always use these APIs even we make x86 specific set_ptes()? I will find a test machine to measure the performance difference of these two versions by using xfs + will-it-scale. Will keep you guys updated. Regards Yin, Fengwei