Received: by 2002:a05:7412:31a9:b0:e2:908c:2ebd with SMTP id et41csp3964017rdb; Thu, 14 Sep 2023 08:00:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFSONVeTyvkkM1FfuC9rdsF1Gc4xg+r4dGRK/EPyrEHMV5JiPVZGAiiXvrlDvTRj+kbOClx X-Received: by 2002:a17:90b:152:b0:274:755b:63b8 with SMTP id em18-20020a17090b015200b00274755b63b8mr1460848pjb.43.1694703608161; Thu, 14 Sep 2023 08:00:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1694703608; cv=none; d=google.com; s=arc-20160816; b=AclqO0YGaML0s5/KUIz5Nnu9YV6YPjxZAcdAy9AeS4TmD33l5EHLDfaYiLOtw1em6x WC+wVyepIGtAh3PA1tXYmyosQnnPzJ2r9j++Q4jMPVV9g34gTpoMUjN9n6wxqMGUHawB 4wEgoSo95c1lbankcDFBuc8qlgA7GyO2QsqEawS1kbMdBHvKRkwfY0Gebh1gQMgJ/utk eVlrDyOvD/VXfcqggBM/cdkVnTwzV2sLV49IYeDc+I/Ieku640cbJrURHOxsZluK8o7p o7kpvyHqUc8WvjXRXfWlXfCUhfFAodfX7G64aEZkk/GqNs+jSbDIaMHGXZiyiuYhT8mU OH3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4wFB6cUb2x9clN9MEsSeQzec66vAcyPthrASIMjg9EY=; fh=jqCbnajAXgJ+s7A1aA7DOHJD13/+EpD442pw8d+Ofss=; b=p9dyHW1nIT0X1TY9jwXPiDfkdo5VUw6GoBEAms/KA132zsnBQd6OtXLIJbNCqmZInl boMfNZoKR/BYU100Xao5tGf0OUtU1v57DY8BtMrDndWAoVEghUFgxOsu5gg5+tOOauHv M1HRHfcl6PvjBX2Og8UPi8dKxMhixVCjbczbCf16O1VAvA1UAdXRaeibk2A+AiwXRRuP BOP0Q1eGoD9xfG8+9avpnAaKcLJ2H4mPpdfn1lkdQkGSAsHDC+leO5Mn1JczxJ9gLVmX OI7ExIpxvK5+JPs2Ckosfx1L+RnChtcUVBrrqfSEC3O73Jfxakd+WSlY832BcmpIdk4K lC7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=V9E4zvsn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id mv19-20020a17090b199300b00262cc36ea3esi1812429pjb.76.2023.09.14.08.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Sep 2023 08:00:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=V9E4zvsn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 1E968822CE85; Wed, 13 Sep 2023 22:20:55 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235684AbjINFUe (ORCPT + 99 others); Thu, 14 Sep 2023 01:20:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235104AbjINFTp (ORCPT ); Thu, 14 Sep 2023 01:19:45 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EAB81FEF; Wed, 13 Sep 2023 22:19:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1694668763; x=1726204763; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WI4PNmnQNqWbUIJ+xrhdRHV/OU0QAbzmppTdHG3/yfg=; b=V9E4zvsnYYAIbtrWW3j6tn9Z5xfUWrHW6BAvD0mlJBQKAO6gkVmhyHd7 x7AXjzC1rW0lMFghYIjrSZdfUuNoDhHFJucV33SSyQ/+G8Z9m/MOFcbHh MJcZMwqGaD9ILWmvUd5jLTsTxfVX0uGNeYb5YiQWtFvF25J96M9MpQD7i 9jZg3rEftqsMmiferujswLHvqY4AYBE8CKapdcWaUSUjx0z57B/rVKNUS fpvP77iMOdTOv3/LgYo2CHWVdlRAmfsbQQOVNaxiIlpy02gs4X9PnF44r N/6vZvLttKXMAzKPRjwiZNm+kNYqCi3Nf412HZuy4pTa/TFW6RHtAlXlQ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10832"; a="382661394" X-IronPort-AV: E=Sophos;i="6.02,145,1688454000"; d="scan'208";a="382661394" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2023 22:17:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10832"; a="779488814" X-IronPort-AV: E=Sophos;i="6.02,145,1688454000"; d="scan'208";a="779488814" Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga001.jf.intel.com with ESMTP; 13 Sep 2023 22:17:41 -0700 From: Xin Li To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, linux-hyperv@vger.kernel.org, kvm@vger.kernel.org, xen-devel@lists.xenproject.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, luto@kernel.org, pbonzini@redhat.com, seanjc@google.com, peterz@infradead.org, jgross@suse.com, ravi.v.shankar@intel.com, mhiramat@kernel.org, andrew.cooper3@citrix.com, jiangshanlai@gmail.com Subject: [PATCH v10 25/38] x86/fred: Add a debug fault entry stub for FRED Date: Wed, 13 Sep 2023 21:47:52 -0700 Message-Id: <20230914044805.301390-26-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230914044805.301390-1-xin3.li@intel.com> References: <20230914044805.301390-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 13 Sep 2023 22:20:55 -0700 (PDT) From: "H. Peter Anvin (Intel)" When occurred on different ring level, i.e., from user or kernel context, #DB needs to be handled on different stack: User #DB on current task stack, while kernel #DB on a dedicated stack. This is exactly how FRED event delivery invokes an exception handler: ring 3 event on level 0 stack, i.e., current task stack; ring 0 event on the #DB dedicated stack specified in the IA32_FRED_STKLVLS MSR. So unlike IDT, the FRED debug exception entry stub doesn't do stack switch. On a FRED system, the debug trap status information (DR6) is passed on the stack, to avoid the problem of transient state. Furthermore, FRED transitions avoid a lot of ugly corner cases the handling of which can, and should be, skipped. The FRED debug trap status information saved on the stack differs from DR6 in both stickiness and polarity; it is exactly in the format which debug_read_clear_dr6() returns for the IDT entry points. Signed-off-by: H. Peter Anvin (Intel) Tested-by: Shan Kang Signed-off-by: Xin Li --- Changes since v9: * Disable #DB to avoid endless recursion and stack overflow when a watchpoint/breakpoint is set in the code path which is executed by #DB handler (Thomas Gleixner). Changes since v1: * call irqentry_nmi_{enter,exit}() in both IDT and FRED debug fault kernel handler (Peter Zijlstra). --- arch/x86/kernel/traps.c | 43 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index c876f1d36a81..848c85208a57 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include #include @@ -934,8 +935,7 @@ static bool notify_debug(struct pt_regs *regs, unsigned long *dr6) return false; } -static __always_inline void exc_debug_kernel(struct pt_regs *regs, - unsigned long dr6) +static noinstr void exc_debug_kernel(struct pt_regs *regs, unsigned long dr6) { /* * Disable breakpoints during exception handling; recursive exceptions @@ -947,6 +947,11 @@ static __always_inline void exc_debug_kernel(struct pt_regs *regs, * * Entry text is excluded for HW_BP_X and cpu_entry_area, which * includes the entry stack is excluded for everything. + * + * For FRED, nested #DB should just work fine. But when a watchpoint or + * breakpoint is set in the code path which is executed by #DB handler, + * it results in an endless recursion and stack overflow. Thus we stay + * with the IDT approach, i.e., save DR7 and disable #DB. */ unsigned long dr7 = local_db_save(); irqentry_state_t irq_state = irqentry_nmi_enter(regs); @@ -976,7 +981,8 @@ static __always_inline void exc_debug_kernel(struct pt_regs *regs, * Catch SYSENTER with TF set and clear DR_STEP. If this hit a * watchpoint at the same time then that will still be handled. */ - if ((dr6 & DR_STEP) && is_sysenter_singlestep(regs)) + if (!cpu_feature_enabled(X86_FEATURE_FRED) && + (dr6 & DR_STEP) && is_sysenter_singlestep(regs)) dr6 &= ~DR_STEP; /* @@ -1008,8 +1014,7 @@ static __always_inline void exc_debug_kernel(struct pt_regs *regs, local_db_restore(dr7); } -static __always_inline void exc_debug_user(struct pt_regs *regs, - unsigned long dr6) +static noinstr void exc_debug_user(struct pt_regs *regs, unsigned long dr6) { bool icebp; @@ -1093,6 +1098,34 @@ DEFINE_IDTENTRY_DEBUG_USER(exc_debug) { exc_debug_user(regs, debug_read_clear_dr6()); } + +#ifdef CONFIG_X86_FRED +/* + * When occurred on different ring level, i.e., from user or kernel + * context, #DB needs to be handled on different stack: User #DB on + * current task stack, while kernel #DB on a dedicated stack. + * + * This is exactly how FRED event delivery invokes an exception + * handler: ring 3 event on level 0 stack, i.e., current task stack; + * ring 0 event on the #DB dedicated stack specified in the + * IA32_FRED_STKLVLS MSR. So unlike IDT, the FRED debug exception + * entry stub doesn't do stack switch. + */ +DEFINE_FREDENTRY_DEBUG(exc_debug) +{ + /* + * FRED #DB stores DR6 on the stack in the format which + * debug_read_clear_dr6() returns for the IDT entry points. + */ + unsigned long dr6 = fred_event_data(regs); + + if (user_mode(regs)) + exc_debug_user(regs, dr6); + else + exc_debug_kernel(regs, dr6); +} +#endif /* CONFIG_X86_FRED */ + #else /* 32 bit does not have separate entry points. */ DEFINE_IDTENTRY_RAW(exc_debug) -- 2.34.1