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[209.85.219.181]) by smtp.gmail.com with ESMTPSA id c17-20020a5b0bd1000000b00d3596aca5bcsm360223ybr.34.2023.09.14.08.26.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Sep 2023 08:26:27 -0700 (PDT) Received: by mail-yb1-f181.google.com with SMTP id 3f1490d57ef6-d81b42a3108so316446276.1; Thu, 14 Sep 2023 08:26:26 -0700 (PDT) X-Received: by 2002:a25:d1d6:0:b0:d19:664:7425 with SMTP id i205-20020a25d1d6000000b00d1906647425mr5526179ybg.27.1694705186564; Thu, 14 Sep 2023 08:26:26 -0700 (PDT) MIME-Version: 1.0 References: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com> <20230912045157.177966-22-claudiu.beznea.uj@bp.renesas.com> <20230912160330.GA864606-robh@kernel.org> In-Reply-To: <20230912160330.GA864606-robh@kernel.org> From: Geert Uytterhoeven Date: Thu, 14 Sep 2023 17:26:14 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 21/37] dt-bindings: clock: add r9a08g045 CPG clocks and resets definitions To: Rob Herring Cc: Claudiu , mturquette@baylibre.com, sboyd@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, ulf.hansson@linaro.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com, quic_bjorande@quicinc.com, arnd@arndb.de, konrad.dybcio@linaro.org, neil.armstrong@linaro.org, nfraprado@collabora.com, rafal@milecki.pl, wsa+renesas@sang-engineering.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Thu, 14 Sep 2023 08:26:46 -0700 (PDT) Hi Rob, On Tue, Sep 12, 2023 at 6:03 PM Rob Herring wrote: > On Tue, Sep 12, 2023 at 07:51:41AM +0300, Claudiu wrote: > > From: Claudiu Beznea > > > > Add RZ/G3S (R9A08G045) Clock Pulse Generator (CPG) core clocks, module > > clocks and resets. > > This is part of the binding, so it can be squashed with the previous > patch. The ack there still stands. Usually we keep it as a separate patch, to be queued in an immutable branch, as it is included by both the clock driver and by DTS, but not by the yaml bindings file. > > Signed-off-by: Claudiu Beznea > > --- > > include/dt-bindings/clock/r9a08g045-cpg.h | 243 ++++++++++++++++++++++ > > 1 file changed, 243 insertions(+) > > create mode 100644 include/dt-bindings/clock/r9a08g045-cpg.h Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds