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[209.85.219.169]) by smtp.gmail.com with ESMTPSA id j73-20020a25234c000000b00babcd913630sm328997ybj.3.2023.09.14.06.12.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Sep 2023 06:12:21 -0700 (PDT) Received: by mail-yb1-f169.google.com with SMTP id 3f1490d57ef6-d8181087dc9so934514276.3; Thu, 14 Sep 2023 06:12:21 -0700 (PDT) X-Received: by 2002:a25:c7d1:0:b0:d5c:4a6a:f5a4 with SMTP id w200-20020a25c7d1000000b00d5c4a6af5a4mr5646812ybe.24.1694697141289; Thu, 14 Sep 2023 06:12:21 -0700 (PDT) MIME-Version: 1.0 References: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com> <20230912045157.177966-13-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20230912045157.177966-13-claudiu.beznea.uj@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 14 Sep 2023 15:12:08 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 12/37] clk: renesas: rzg2l: reduce the critical area To: Claudiu Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, ulf.hansson@linaro.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com, quic_bjorande@quicinc.com, arnd@arndb.de, konrad.dybcio@linaro.org, neil.armstrong@linaro.org, nfraprado@collabora.com, rafal@milecki.pl, wsa+renesas@sang-engineering.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Thu, 14 Sep 2023 06:12:34 -0700 (PDT) Hi Claudiu, On Tue, Sep 12, 2023 at 6:52 AM Claudiu wrote: > From: Claudiu Beznea > > spinlock in rzg2l_mod_clock_endisable() is intended to protect the accesses > to hardware register. There is no need to protect the instructions that set > temporary variable which will be then written to register. Thus limit the > spinlock only to the hardware register access. > > Signed-off-by: Claudiu Beznea Thanks for your patch! > --- a/drivers/clk/renesas/rzg2l-cpg.c > +++ b/drivers/clk/renesas/rzg2l-cpg.c > @@ -912,13 +912,13 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) > > dev_dbg(dev, "CLK_ON %u/%pC %s\n", CLK_ON_R(reg), hw->clk, > enable ? "ON" : "OFF"); > - spin_lock_irqsave(&priv->rmw_lock, flags); > > value = bitmask << 16; > if (enable) > value |= bitmask; > - writel(value, priv->base + CLK_ON_R(reg)); > > + spin_lock_irqsave(&priv->rmw_lock, flags); > + writel(value, priv->base + CLK_ON_R(reg)); > spin_unlock_irqrestore(&priv->rmw_lock, flags); After this, it becomes obvious there is nothing to protect at all, so the locking can just be removed from this function? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds