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[2620:137:e000::3:3]) by mx.google.com with ESMTPS id s1-20020a17090aad8100b002465d98f18csi4020418pjq.170.2023.09.14.09.23.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Sep 2023 09:23:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=amWJ5kA7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 4AD3981A9ED8; Thu, 14 Sep 2023 09:21:07 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238257AbjINQU6 (ORCPT + 99 others); Thu, 14 Sep 2023 12:20:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236974AbjINQU5 (ORCPT ); Thu, 14 Sep 2023 12:20:57 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FD411FC8; Thu, 14 Sep 2023 09:20:53 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B319BC433CA; Thu, 14 Sep 2023 16:20:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1694708452; bh=Iz3OaOq7Jg3c1k6+q2I0zpdnqpko+95FwExIqjkenD0=; h=In-Reply-To:References:Subject:From:Cc:To:Date:From; b=amWJ5kA7hssVaXF52M2JWRhuM24paxEfVHoyO8i16sRm1p6hKsaBklVQWnDFuqi4P 1wwiUeNAPex238n8USkb1lB9ZAcWs6g4aUI7DoCibiyqAkV0yC6/qGnbVb/TOkygdY c4NEqUMAysIOELbbIbz8sly0D3eKpmTZhdmn6cLgXIhXKgzDKNEIDc9llQPOt1ufUM W+2G4kzWuVF34rQWA0wa+MyfWGovzAJlHEzkoDLb0sBKFNaaLPE8McmE7HdzqtXgRB QjRiP+rLsc+B2RT9LOARgp3ct8O6nrv56m5H6Bw5qTcNhWpjK7/6IYDVMvoADQO3G+ IWllD+t5RBvVQ== Message-ID: <539752971c7a61ce7a5deddc1478686a.sboyd@kernel.org> Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <20230913175612.8685-1-danila@jiaxyga.com> References: <20230913175612.8685-1-danila@jiaxyga.com> Subject: Re: [PATCH] clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_src From: Stephen Boyd Cc: danila@jiaxyga.com, adomerlee@gmail.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org To: Danila Tikhonov , agross@kernel.org, andersson@kernel.org, dkatraga@codeaurora.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, quic_tdas@quicinc.com, vkoul@kernel.org Date: Thu, 14 Sep 2023 09:20:50 -0700 User-Agent: alot/0.10 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 14 Sep 2023 09:21:07 -0700 (PDT) X-Spam-Status: No, score=-1.2 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Quoting Danila Tikhonov (2023-09-13 10:56:11) > Set .flags =3D CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg > didn't update its configuration" error. >=20 > Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver = for SM8150") > Tested-by: Arseniy Velikanov > Signed-off-by: Danila Tikhonov > --- > drivers/clk/qcom/gcc-sm8150.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c > index 41ab210875fb..05d115c52dfe 100644 > --- a/drivers/clk/qcom/gcc-sm8150.c > +++ b/drivers/clk/qcom/gcc-sm8150.c > @@ -774,7 +774,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src =3D { > .name =3D "gcc_sdcc2_apps_clk_src", > .parent_data =3D gcc_parents_6, > .num_parents =3D ARRAY_SIZE(gcc_parents_6), > - .flags =3D CLK_SET_RATE_PARENT, > + .flags =3D CLK_OPS_PARENT_ENABLE, > .ops =3D &clk_rcg2_floor_ops, In what case are we getting the rcg stuck? I thought that you could write the rcg registers while the parent was off and switch to that parent if the parent isn't enabled and it wouldn't get stuck.