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Thu, 14 Sep 2023 04:22:31 -0700 (PDT) On 9/14/2023 4:48 PM, Peter Zijlstra wrote: > On Thu, Sep 14, 2023 at 02:30:43AM -0700, Breno Leitao wrote: >> On Thu, Sep 14, 2023 at 11:12:34AM +0200, Peter Zijlstra wrote: >>> On Thu, Sep 14, 2023 at 02:25:40PM +0530, Sandipan Das wrote: >> >>>> I agree with using WARN_ON_ONCE() to make this less intrusive. >>> >>> Could you send a patch that AMD is happy with? >> >> Why the current patch is not good enough? > > Sandipan, can you answer this? I don't tihnk I'm qualified to speak for > the AMD pmu and certainly I don't have insight into their design future. Hi Breno, Functionally, the patch looks good to me and I will be reusing it without any change to the authorship. However, as Peter suggested, I wanted to add a message to prompt users to update the microcode and also call out the required patch levels in the commit message since different Zen 4 variants and steppings use different microcode. Here's what I plan to send. diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index abadd5f23425..186a124bb3c0 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -909,6 +909,13 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs) status &= ~GLOBAL_STATUS_LBRS_FROZEN; } + if (status & ~amd_pmu_global_cntr_mask) + pr_warn_once("Unknown status bits are set (0x%llx), please consider updating microcode\n", + status); + + /* Clear any reserved bits set by buggy microcode */ + status &= amd_pmu_global_cntr_mask; + for (idx = 0; idx < x86_pmu.num_counters; idx++) { if (!test_bit(idx, cpuc->active_mask)) continue; -- Hi Peter, There is another case where users will see warnings but the patch to fix it (link below) is yet to be reviewed. May I rebase and resend it along with the above? https://lore.kernel.org/all/20230613105809.524535-1-sandipan.das@amd.com/