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Peter Anvin" , leit@fb.com, dcostantino@meta.com, "open list:PERFORMANCE EVENTS SUBSYSTEM" , "open list:PERFORMANCE EVENTS SUBSYSTEM" , ananth.narayan@amd.com, Ravi Bangoria , Michael Petlan Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Thu, 14 Sep 2023 01:45:45 -0700 (PDT) Hi Sandipan, here is the info from /proc/cpuinfo vendor_id : AuthenticAMD cpu family : 25 model : 160 model name : AMD EPYC 9754 128-Core Processor stepping : 2 microcode : 0xaa0020f >2. Microcode patch level Is it the microcode string from cpuinfo provided above, or are you looking for something else? Thanks! Jirka On Wed, Sep 13, 2023 at 6:19=E2=80=AFPM Sandipan Das = wrote: > > Hi Jirka, > > Can you please share the following? > > 1. Family, Model and Stepping of the processor > 2. Microcode patch level > On 9/13/2023 8:00 PM, Jirka Hladky wrote: > > Hi Sandipan, > > > > Is there any update on this issue? We have hit the issue, and it makes > > the server pretty unusable due to the thousands of Call Traces being > > logged. > > > > Thanks a lot! > > Jirka > > > > > > On Fri, Jun 16, 2023 at 5:34=E2=80=AFPM Peter Zijlstra wrote: > >> > >> On Fri, Jun 16, 2023 at 08:13:22PM +0530, Sandipan Das (AMD) wrote: > >>> The reserved bits should never be set. The purpose of the WARN_ON() i= s to catch such anomalies. > >>> I am working out the details with Breno and will report back with a r= esolution. > >> > >> Thanks! > >> > > > > > --=20 -Jirka