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References: <20230914064922.3986-1-zajec5@gmail.com> <28fad55f-1253-deb2-9615-b32746129664@gmail.com>
In-Reply-To: <28fad55f-1253-deb2-9615-b32746129664@gmail.com>
From:   Scott Branden <scott.branden@broadcom.com>
Date:   Thu, 14 Sep 2023 14:30:58 -0700
Message-ID: <CA+Jzhd+HLoUDifQQ5vF7m66X3rsk1Bk2yx_0h6eSzaUwXVa72w@mail.gmail.com>
Subject: Re: [PATCH] nvmem: brcm_nvram: store a copy of NVRAM content
To:     Florian Fainelli <f.fainelli@gmail.com>
Cc:     =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= <zajec5@gmail.com>,
        Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
        linux-mtd@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= <rafal@milecki.pl>,
        =?UTF-8?B?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>,
        Florian Fainelli <florian.fainelli@broadcom.com>
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On Thu, Sep 14, 2023 at 2:26=E2=80=AFPM Florian Fainelli <f.fainelli@gmail.=
com> wrote:
>
> On 9/13/23 23:49, Rafa=C5=82 Mi=C5=82ecki wrote:
> > From: Rafa=C5=82 Mi=C5=82ecki <rafal@milecki.pl>
> >
> > This driver uses MMIO access for reading NVRAM from a flash device.
> > Underneath there is a flash controller that reads data and provides
> > mapping window.
> >
> > Using MMIO interface affects controller configuration and may break rea=
l
> > controller driver. It was reported by multiple users of devices with
> > NVRAM stored on NAND.
> >
> > Modify driver to read & cache all NVRAM content during init and use tha=
t
> > copy to provide NVMEM data when requested.
> >
> > Link: https://lore.kernel.org/linux-mtd/CACna6rwf3_9QVjYcM+847biTX=3DK0=
EoWXuXcSMkJO1Vy_5vmVqA@mail.gmail.com/
> > Cc: Ar=C4=B1n=C3=A7 =C3=9CNAL <arinc.unal@arinc9.com>
> > Cc: Florian Fainelli <florian.fainelli@broadcom.com>
> > Cc: Scott Branden <scott.branden@broadcom.com>
> > Signed-off-by: Rafa=C5=82 Mi=C5=82ecki <rafal@milecki.pl>
> > ---
> [snip]
> > -     priv->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &r=
es);
> > -     if (IS_ERR(priv->base))
> > -             return PTR_ERR(priv->base);
> > +     base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res);
> > +     if (IS_ERR(base))
> > +             return PTR_ERR(base);
> > +
> > +     priv->size =3D resource_size(res);
> > +
> > +     priv->data =3D devm_kzalloc(dev, priv->size, GFP_KERNEL);
>
> These can conceivably quite big data structures, how about using kvmalloc=
()?
Why do we even need to expose MMIO interface to NAND though?  Why not
always go through the controller driver.  I don't see how the MMIO
access would be used given bad blocks aren't handled?
> --
> Florian
>

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