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From:   Suren Baghdasaryan <surenb@google.com>
Date:   Thu, 14 Sep 2023 21:15:31 -0700
Message-ID: <CAJuCfpESQFWPuGS0_8swoM3iGEUbpeOH7Z9dvsPJZ5dJ1ENDDg@mail.gmail.com>
Subject: Re: [PATCH 2/3] userfaultfd: UFFDIO_REMAP uABI
To:     Nadav Amit <nadav.amit@gmail.com>
Cc:     Andrew Morton <akpm@linux-foundation.org>, viro@zeniv.linux.org.uk,
        brauner@kernel.org, shuah@kernel.org,
        Andrea Arcangeli <aarcange@redhat.com>, lokeshgidra@google.com,
        Peter Xu <peterx@redhat.com>,
        David Hildenbrand <david@redhat.com>,
        Hugh Dickins <hughd@google.com>, mhocko@suse.com,
        Axel Rasmussen <axelrasmussen@google.com>,
        Mike Rapoport <rppt@kernel.org>,
        Matthew Wilcox <willy@infradead.org>, Liam.Howlett@oracle.com,
        Jann Horn <jannh@google.com>, zhangpeng362@huawei.com,
        bgeffon@google.com, kaleshsingh@google.com, ngeoffray@google.com,
        jdduke@google.com, linux-mm <linux-mm@kvack.org>,
        linux-fsdevel@vger.kernel.org,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
        linux-kselftest@vger.kernel.org, kernel-team@android.com
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On Fri, Sep 15, 2023 at 4:04=E2=80=AFAM Nadav Amit <nadav.amit@gmail.com> w=
rote:
>
>
>
> > On Sep 14, 2023, at 8:28 PM, Suren Baghdasaryan <surenb@google.com> wro=
te:
> >
> > On Thu, Sep 14, 2023 at 2:57=E2=80=AFPM Nadav Amit <nadav.amit@gmail.co=
m> wrote:
> >>
> >>
> >>> On Sep 14, 2023, at 8:26 AM, Suren Baghdasaryan <surenb@google.com> w=
rote:
> >>>
> >>> +     if (!pte_same(ptep_clear_flush(src_vma, src_addr, src_pte),
> >>> +             orig_src_pte))
> >>> +             BUG_ON(1);
> >>
> >> Just a minor detail regarding these few lines:
> >>
> >> Besides the less-than-ideal use of BUG_ON() here, I think that this co=
de
> >> assumes that the PTE cannot change at this point. However, as the PTE =
was
> >> still mapped at this point, I think the access and dirty bits can be s=
et.
> >
> > At this point we are holding PTLs for both PTEs (see
> > double_pt_lock()).  Can a PTE be modified from under us in this
> > situation?
>
> PTEs has several parts: access-control bits (e.g., writable), physical
> frame number, software-only bits and log-bits. The log-bits, which are
> =E2=80=9Caccess=E2=80=9D and =E2=80=9Cdirty=E2=80=9D on x86, track whethe=
r the PTE has ever been used
> for translation or write correspondingly.
>
> Without getting into all the subtleties (e.g., =E2=80=9Caccess" can be se=
t
> speculatively even if no actual access take place), as long as the PTE
> is present, it might be used for access (and write if it is writable)
> by other cores. The page-table locks are irrelevant here, because the
> PTE is not updated by software, but it is updated by the CPU itself
> during the page-walk/write.

Ah, I see. I believe Jann also pointed this out in one of his comments
and I didn't realize that. Thanks for the note! I'll see how I can
rework this.

>
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