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Subject: Re: [PATCH net-next v3 0/2] Add Half Duplex support for ICSSG Driver
From:   patchwork-bot+netdevbpf@kernel.org
Message-Id: <169478282660.10241.3855414468809647924.git-patchwork-notify@kernel.org>
Date:   Fri, 15 Sep 2023 13:00:26 +0000
References: <20230913091011.2808202-1-danishanwar@ti.com>
In-Reply-To: <20230913091011.2808202-1-danishanwar@ti.com>
To:     MD Danish Anwar <danishanwar@ti.com>
Cc:     andrew@lunn.ch, rogerq@ti.com, conor+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org,
        pabeni@redhat.com, kuba@kernel.org, edumazet@google.com,
        davem@davemloft.net, vigneshr@ti.com, horms@kernel.org,
        linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        netdev@vger.kernel.org, srk@ti.com, r-gunasekaran@ti.com
Precedence: bulk

Hello:

This series was applied to netdev/net-next.git (main)
by David S. Miller <davem@davemloft.net>:

On Wed, 13 Sep 2023 14:40:09 +0530 you wrote:
> This series adds support for half duplex operation for ICSSG driver.
> 
> In order to support half-duplex operation at 10M and 100M link speeds, the
> PHY collision detection signal (COL) should be routed to ICSSG GPIO pin
> (PRGx_PRU0/1_GPI10) so that firmware can detect collision signal and apply
> the CSMA/CD algorithm applicable for half duplex operation. A DT property,
> "ti,half-duplex-capable" is introduced for this purpose in the first patch
> of the series. If board has PHY COL pin conencted to PRGx_PRU1_GPIO10,
> this DT property can be added to eth node of ICSSG, MII port to support
> half duplex operation at that port.
> 
> [...]

Here is the summary with links:
  - [net-next,v3,1/2] dt-bindings: net: Add documentation for Half duplex support.
    https://git.kernel.org/netdev/net-next/c/927c568d6212
  - [net-next,v3,2/2] net: ti: icssg-prueth: Add support for half duplex operation
    https://git.kernel.org/netdev/net-next/c/0a205f0fe8dd

You are awesome, thank you!
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