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From:   Thomas Gleixner <tglx@linutronix.de>
To:     K Prateek Nayak <kprateek.nayak@amd.com>,
        LKML <linux-kernel@vger.kernel.org>
Cc:     x86@kernel.org, Tom Lendacky <thomas.lendacky@amd.com>,
        Andrew Cooper <andrew.cooper3@citrix.com>,
        Arjan van de Ven <arjan@linux.intel.com>,
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        Dimitri Sivanich <dimitri.sivanich@hpe.com>,
        Michael Kelley <mikelley@microsoft.com>,
        Wei Liu <wei.liu@kernel.org>, Pu Wen <puwen@hygon.cn>,
        Qiuxu Zhuo <qiuxu.zhuo@intel.com>,
        Sohil Mehta <sohil.mehta@intel.com>,
        Gautham Shenoy <gautham.shenoy@amd.com>
Subject: Re: [patch V4 24/41] x86/cpu: Provide cpu_init/parse_topology()
In-Reply-To: <011011ee-4f83-3545-4ca2-55bc0bef284a@amd.com>
References: <20230814085006.593997112@linutronix.de>
 <20230814085113.471353147@linutronix.de>
 <934072fe-eca2-44df-94e7-9fed1dc8b502@amd.com> <87r0nn8ots.ffs@tglx>
 <4a4d5a89-b024-ea49-8740-1f3aef412c15@amd.com>
 <011011ee-4f83-3545-4ca2-55bc0bef284a@amd.com>
Date:   Fri, 15 Sep 2023 13:46:46 +0200
Message-ID: <87led71wwp.ffs@tglx>
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Prateek!

On Thu, Sep 14 2023 at 14:50, K. Prateek Nayak wrote:
> On 8/28/2023 7:58 PM, K Prateek Nayak wrote:
> o Logical Processor : A processor core provides one or more logical
> 	    processors sharing execution resources. The
> 	    LOGICAL_PROCESSOR_ID sub-field distinguishes logical
> 	    processors in a core. The width of this bit field is
> 	    non-zero if a processor core provides more than one logical
> 	    processors.
> """
>
> So some questions to Intel folks to determine whether mapping AMD's
> Complex to Tile makes sense or not:
>
> - What are the "certain resources" a group of module / tile share?
>
> - Module and Tile both use the phrase "set of cores" in their
>   description. Does this mean their existence is mutually exclusive?

That's definitely a good question.

> AMD's Complex (CCX) marks the L3 cache boundary. If either of the
> "certain resources" refer to L3 cache, then Complex can be safely mapped
> to the respective level without any fear of misinterpretation of the
> characteristics.

I don't think it's a good idea to try deducing cache hierarchy from the
basic topology. The boundaries have changed over time and AMD has made
it impossible on older CPUs to use the CPU topology for that.

I tried to do that and gave up because I realized that we need both and
then do the proper association by combining the information.

> Also, I do not see a "DieGrp" domain in the "x86_topology_domains". Is
> this because of the lack of "software visible" aspect of it despite its
> possible existence?

No. It's subsumed by the package domain. Let me look at the mechanics
some more to make this more obvious.

Thanks,

        tglx