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Date:   Fri, 15 Sep 2023 10:03:32 -0500
From:   Rob Herring <robh@kernel.org>
To:     Conor Dooley <conor@kernel.org>
Cc:     Wang Chen <unicornxw@gmail.com>, linux-riscv@lists.infradead.org,
        aou@eecs.berkeley.edu, krzysztof.kozlowski+dt@linaro.org,
        palmer@dabbelt.com, paul.walmsley@sifive.com,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        jszhang@kernel.org, guoren@kernel.org, chao.wei@sophgo.com,
        xiaoguang.xing@sophgo.com, Wang Chen <wangchen20@iscas.ac.cn>
Subject: Re: [PATCH 04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles
Message-ID: <20230915150332.GA3719864-robh@kernel.org>
References: <20230915072333.117991-1-wangchen20@iscas.ac.cn>
 <20230915-muster-viability-93d7d4ec2b49@spud>
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On Fri, Sep 15, 2023 at 03:11:43PM +0100, Conor Dooley wrote:
> On Fri, Sep 15, 2023 at 03:23:33PM +0800, Wang Chen wrote:
> > The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
> > Notably, the C920 core is used in the SOPHGO SG2042 SoC.
> > 
> > Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
> > Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> 
> I figure this is missing a From: or Co-developed-by line.

From: (author) as 2 authors for 1 line change is questionable.

The sender's email should be the last S-o-b. So like this:

From: Xiaoguang Xing <xiaoguang.xing@sophgo.com>

...

Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>


> 
> > ---
> >  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index 38c0b5213736..185a0191bad6 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -47,6 +47,7 @@ properties:
> >                - sifive,u74-mc
> >                - thead,c906
> >                - thead,c910
> > +              - thead,c920
> >            - const: riscv
> >        - items:
> >            - enum:
> > -- 
> > 2.25.1
> >