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Date:   Fri, 15 Sep 2023 07:04:56 -0700
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Subject: Re: [patch V4 24/41] x86/cpu: Provide cpu_init/parse_topology()
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To:     Peter Zijlstra <peterz@infradead.org>,
        K Prateek Nayak <kprateek.nayak@amd.com>
Cc:     Thomas Gleixner <tglx@linutronix.de>,
        LKML <linux-kernel@vger.kernel.org>, x86@kernel.org,
        Tom Lendacky <thomas.lendacky@amd.com>,
        Andrew Cooper <andrew.cooper3@citrix.com>,
        Huang Rui <ray.huang@amd.com>, Juergen Gross <jgross@suse.com>,
        Dimitri Sivanich <dimitri.sivanich@hpe.com>,
        Michael Kelley <mikelley@microsoft.com>,
        Wei Liu <wei.liu@kernel.org>, Pu Wen <puwen@hygon.cn>,
        Qiuxu Zhuo <qiuxu.zhuo@intel.com>,
        Sohil Mehta <sohil.mehta@intel.com>,
        Gautham Shenoy <gautham.shenoy@amd.com>
References: <20230814085006.593997112@linutronix.de>
 <20230814085113.471353147@linutronix.de>
 <934072fe-eca2-44df-94e7-9fed1dc8b502@amd.com> <87r0nn8ots.ffs@tglx>
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 <abb65e60-4e8b-7036-4401-d21b273b6d67@linux.intel.com>
 <6f101718-7ee1-1c3d-3e0a-3aa708928ecd@amd.com>
 <20230915115428.GD6721@noisy.programming.kicks-ass.net>
From:   Arjan van de Ven <arjan@linux.intel.com>
In-Reply-To: <20230915115428.GD6721@noisy.programming.kicks-ass.net>
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On 9/15/2023 4:54 AM, Peter Zijlstra wrote:
> On Tue, Aug 29, 2023 at 08:46:14AM +0530, K Prateek Nayak wrote:
>> Hello Arjan,
>>
>> On 8/28/2023 8:04 PM, Arjan van de Ven wrote:
>>> On 8/28/2023 7:28 AM, K Prateek Nayak wrote:
>>>>>      - Are these really different between AMD and Intel or is this some
>>>>>        naming convention issue which needs to be resolved?
>>>>      They do have different characteristics since, on Sapphire
>>>>      Rapids, the LLC is at a socket boundary despite having multiple
>>>>      tiles. (Please correct me if I'm wrong, I'm going off of
>>>>      llc_id shared in this report by Qiuxu Zhuo -
>>>>      https://lore.kernel.org/all/20230809161219.83084-1-qiuxu.zhuo@intel.com/)
>>>>
>>>
>>> Sapphire reports itself as 1 tile though (since logically it is) as far as I know
>>>
>>
>> I believe there are some variants with multiple tiles, at least the
>> following press-release suggests that:
>>
>>    https://www.intc.com/news-events/press-releases/detail/1598/intel-launches-4th-gen-xeon-scalable-processors-max-series
>>
>> specifically "... combining up to four Intel 7-built tiles on a single
>> package, connected using Intel EMIB ...". Perhaps the one from Qiuxu
>> Zhuo's report does not contain multiple tiles.
> 
> I think what Arjan was saying that despite them being build using
> multipe physical tiles, they describe themselves, in the topology leave,
> as being a single tile.

and more than that -- from a software perspective, they truely act as if they are 1 tile
(you can do SNC to break that sort of but that's not default and has its own list of downsides)