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 <20230915-muster-viability-93d7d4ec2b49@spud> <20230915150332.GA3719864-robh@kernel.org>
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From:   Chen Wang <unicornxw@gmail.com>
Date:   Sat, 16 Sep 2023 08:46:57 +0800
Message-ID: <CAHAQgRAtFBvoKbfL266cjUNnhSCM4UkU=g6n++7XXXeKOXR8yw@mail.gmail.com>
Subject: Re: [PATCH 04/12] dt-bindings: riscv: Add T-HEAD C920 compatibles
To:     Rob Herring <robh@kernel.org>
Cc:     Conor Dooley <conor@kernel.org>, linux-riscv@lists.infradead.org,
        aou@eecs.berkeley.edu, krzysztof.kozlowski+dt@linaro.org,
        palmer@dabbelt.com, paul.walmsley@sifive.com,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        jszhang@kernel.org, guoren@kernel.org, chao.wei@sophgo.com,
        xiaoguang.xing@sophgo.com, Wang Chen <wangchen20@iscas.ac.cn>
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Thanks for your detailed clarification, Rob. I'll pay attention next time.
Regards,

unicornx

Rob Herring <robh@kernel.org> =E4=BA=8E2023=E5=B9=B49=E6=9C=8815=E6=97=A5=
=E5=91=A8=E4=BA=94 23:03=E5=86=99=E9=81=93=EF=BC=9A
>
> On Fri, Sep 15, 2023 at 03:11:43PM +0100, Conor Dooley wrote:
> > On Fri, Sep 15, 2023 at 03:23:33PM +0800, Wang Chen wrote:
> > > The C920 is RISC-V CPU cores from T-HEAD Semiconductor.
> > > Notably, the C920 core is used in the SOPHGO SG2042 SoC.
> > >
> > > Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
> > > Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> >
> > I figure this is missing a From: or Co-developed-by line.
>
> From: (author) as 2 authors for 1 line change is questionable.
>
> The sender's email should be the last S-o-b. So like this:
>
> From: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
>
> ...
>
> Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com>
> Signed-off-by: Wang Chen <wangchen20@iscas.ac.cn>
>
>
> >
> > > ---
> > >  Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Docu=
mentation/devicetree/bindings/riscv/cpus.yaml
> > > index 38c0b5213736..185a0191bad6 100644
> > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > @@ -47,6 +47,7 @@ properties:
> > >                - sifive,u74-mc
> > >                - thead,c906
> > >                - thead,c910
> > > +              - thead,c920
> > >            - const: riscv
> > >        - items:
> > >            - enum:
> > > --
> > > 2.25.1
> > >
>
>