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[209.85.128.175]) by smtp.gmail.com with ESMTPSA id dt9-20020a05690c250900b0058ddb62f99bsm1685821ywb.38.2023.09.18.00.00.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 18 Sep 2023 00:00:28 -0700 (PDT) Received: by mail-yw1-f175.google.com with SMTP id 00721157ae682-59bc956b029so39683977b3.2; Mon, 18 Sep 2023 00:00:28 -0700 (PDT) X-Received: by 2002:a0d:d808:0:b0:59b:cff1:a8eb with SMTP id a8-20020a0dd808000000b0059bcff1a8ebmr7661269ywe.34.1695020428210; Mon, 18 Sep 2023 00:00:28 -0700 (PDT) MIME-Version: 1.0 References: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com> <20230912045157.177966-23-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Mon, 18 Sep 2023 09:00:16 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 22/37] clk: renesas: add minimal boot support for RZ/G3S SoC To: claudiu beznea Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, ulf.hansson@linaro.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com, quic_bjorande@quicinc.com, arnd@arndb.de, konrad.dybcio@linaro.org, neil.armstrong@linaro.org, nfraprado@collabora.com, rafal@milecki.pl, wsa+renesas@sang-engineering.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 18 Sep 2023 00:01:39 -0700 (PDT) Hi Claudiu, On Mon, Sep 18, 2023 at 8:20 AM claudiu beznea wrote: > On 15.09.2023 15:52, Geert Uytterhoeven wrote: > > On Tue, Sep 12, 2023 at 6:53 AM Claudiu wrote: > >> From: Claudiu Beznea > >> > >> Add minimal clock and reset support for RZ/G3S SoC to be able to boot > >> Linux from SD Card/eMMC. This includes necessary core clocks for booting > >> and GIC, SCIF, GPIO, SD0 mod clocks and resets. > >> > >> Signed-off-by: Claudiu Beznea > > > > Thanks for your patch! > > > >> --- /dev/null > >> +++ b/drivers/clk/renesas/r9a08g045-cpg.c > >> @@ -0,0 +1,217 @@ > >> +// SPDX-License-Identifier: GPL-2.0 > >> +/* > >> + * RZ/G3S CPG driver > >> + * > >> + * Copyright (C) 2023 Renesas Electronics Corp. > >> + */ > >> + > >> +#include > >> +#include > >> +#include > >> +#include > >> + > >> +#include > >> + > >> +#include "rzg2l-cpg.h" > >> + > >> +/* RZ/G3S Specific registers. */ > >> +#define G3S_CPG_PL2_DDIV (0x204) > >> +#define G3S_CPG_SDHI_DDIV (0x218) > >> +#define G3S_CPG_PLL_DSEL (0x240) > >> +#define G3S_CPG_SDHI_DSEL (0x244) > >> +#define G3S_CLKSELSTATUS (0x284) > >> + > >> +/* RZ/G3S Specific division configuration. */ > >> +#define G3S_DIVPL2B DDIV_PACK(G3S_CPG_PL2_DDIV, 4, 3) > >> +#define G3S_DIV_SDHI0 DDIV_PACK(G3S_CPG_SDHI_DDIV, 0, 1) > >> + > >> +/* RZ/G3S Clock status configuration. */ > >> +#define G3S_DIVPL1A_STS DDIV_PACK(CPG_CLKSTATUS, 0, 1) > >> +#define G3S_DIVPL2B_STS DDIV_PACK(CPG_CLKSTATUS, 5, 1) > >> +#define G3S_DIVPL3A_STS DDIV_PACK(CPG_CLKSTATUS, 8, 1) > >> +#define G3S_DIVPL3B_STS DDIV_PACK(CPG_CLKSTATUS, 9, 1) > >> +#define G3S_DIVPL3C_STS DDIV_PACK(CPG_CLKSTATUS, 10, 1) > >> +#define G3S_DIV_SDHI0_STS DDIV_PACK(CPG_CLKSTATUS, 24, 1) > > > > The register at offset 0x280 is called CPG_CLKDIVSTATUS, so > > you probably want to add and use a G3S-specific definition. > > I just used the already definition as there is no conflict at the moment, > it points to the same offset and is almost identical in name. With this > would you still prefer to have it separately ? I think that would be clearer for the casual reader. On RZ/G2L, there is a single CPG_CLKSTATUS register to monitor frequency dividers and selectors. On RZ/G3S, this register was split into separate registers to monitor frequency dividers (CPG_CLKDIVSTATUS) and selectors (CPG_CLKSELSTATUS). You had to add a new definition for the latter anyway. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds