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Mon, 18 Sep 2023 07:42:53 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38I7gqMm015793 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 18 Sep 2023 07:42:52 GMT Received: from [10.216.25.71] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Mon, 18 Sep 2023 00:42:45 -0700 Message-ID: <961b0ad4-baac-4ca4-bc2a-7dae6f129e6f@quicinc.com> Date: Mon, 18 Sep 2023 13:12:42 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v11 10/13] usb: dwc3: qcom: Add multiport suspend/resume support for wrapper Content-Language: en-US To: Konrad Dybcio , Thinh Nguyen , Greg Kroah-Hartman , Philipp Zabel , Andy Gross , "Bjorn Andersson" , Rob Herring , "Krzysztof Kozlowski" , Felipe Balbi , Wesley Cheng , Johan Hovold , Mathias Nyman CC: , , , , , , , , References: <20230828133033.11988-1-quic_kriskura@quicinc.com> <20230828133033.11988-11-quic_kriskura@quicinc.com> <825bc60b-2067-43e2-8b43-9d38b7cebf02@linaro.org> From: Krishna Kurapati PSSNV In-Reply-To: <825bc60b-2067-43e2-8b43-9d38b7cebf02@linaro.org> Content-Type: text/plain; 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Mon, 18 Sep 2023 00:45:32 -0700 (PDT) On 9/15/2023 7:18 PM, Konrad Dybcio wrote: >> >> -#define PWR_EVNT_IRQ_STAT_REG 0x58 >> +#define PWR_EVNT_IRQ1_STAT_REG 0x58 >> +#define PWR_EVNT_IRQ2_STAT_REG 0x1dc >> +#define PWR_EVNT_IRQ3_STAT_REG 0x228 >> +#define PWR_EVNT_IRQ4_STAT_REG 0x238 >> + >> #define PWR_EVNT_LPM_IN_L2_MASK BIT(4) >> #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) >> >> @@ -107,6 +111,19 @@ struct dwc3_qcom { >> int num_ports; >> }; >> >> +/* >> + * SA8295 has 4 power event IRQ STAT registers to be checked >> + * during suspend resume. >> + */ > But this driver supports much more than just SA8295? > Yes. Other than SA8295, all single port controllers and SA8195(2 port controller), have these reigsters. The rational behind adding this array was that depending on num_ports, any controller can access its required pwr_event_irq_stat register and loop in the suspend/resume code would take care of it. Perhaps I can change the comments to indicate that the array would be used by all controllers and not just SA8295. >> +#define NUM_PWR_EVENT_STAT_REGS 4 >> + >> +static u32 pwr_evnt_irq_stat_reg_offset[NUM_PWR_EVENT_STAT_REGS] = { >> + PWR_EVNT_IRQ1_STAT_REG, >> + PWR_EVNT_IRQ2_STAT_REG, >> + PWR_EVNT_IRQ3_STAT_REG, >> + PWR_EVNT_IRQ4_STAT_REG, >> +}; >> + >> static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val) >> { >> u32 reg; >> @@ -440,15 +457,19 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) >> >> static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) >> { >> + u8 num_ports; > Maybe I'm picky, but I'm not sure defining a variable for > a single use of an object with a rather short name > (qcom->num_ports) is justified, here and below.. > Sure, will replace num_ports with (qcom->num_ports) and remove the extra variable. Regards, Krishna,