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[2620:137:e000::3:6]) by mx.google.com with ESMTPS id 5-20020a630d45000000b0055be9543340si7823740pgn.872.2023.09.18.05.37.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Sep 2023 05:37:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=renesas.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id B889C8072F40; Mon, 18 Sep 2023 05:25:52 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241962AbjIRMYv (ORCPT + 99 others); Mon, 18 Sep 2023 08:24:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242017AbjIRMYi (ORCPT ); Mon, 18 Sep 2023 08:24:38 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1DB869F; Mon, 18 Sep 2023 05:24:28 -0700 (PDT) X-IronPort-AV: E=Sophos;i="6.02,156,1688396400"; d="scan'208";a="180128606" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 18 Sep 2023 21:24:28 +0900 Received: from localhost.localdomain (unknown [10.226.92.107]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 9B45C41F6AEF; Mon, 18 Sep 2023 21:24:25 +0900 (JST) From: Biju Das To: Thomas Gleixner , Marc Zyngier Cc: Biju Das , Lad Prabhakar , Claudiu Beznea , Geert Uytterhoeven , Biju Das , linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH 3/3] irqchip: renesas-rzg2l: Fix irq storm with edge trigger detection for TINT Date: Mon, 18 Sep 2023 13:24:11 +0100 Message-Id: <20230918122411.237635-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230918122411.237635-1-biju.das.jz@bp.renesas.com> References: <20230918122411.237635-1-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 18 Sep 2023 05:25:53 -0700 (PDT) In case of edge trigger detection, enabling the TINT source causes a phantum interrupt that leads to irq storm. So clear the phantum interrupt in rzg2l_irqc_irq_enable(). This issue is observed when the irq handler disables the interrupts using disable_irq_nosync() and scheduling a work queue and in the work queue, re-enabling the interrupt with enable_irq(). Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Biju Das Tested-by: Claudiu Beznea --- drivers/irqchip/irq-renesas-rzg2l.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 33a22bafedcd..78a9e90512a6 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -144,6 +144,12 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) reg = readl_relaxed(priv->base + TSSR(tssr_index)); reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset); writel_relaxed(reg, priv->base + TSSR(tssr_index)); + /* + * In case of edge trigger detection, enabling the TINT source + * cause a phantum interrupt that leads to irq storm. So clear + * the phantum interrupt. + */ + rzg2l_tint_eoi(d); raw_spin_unlock(&priv->lock); irq_chip_unmask_parent(d); } -- 2.25.1