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X-IronPort-AV: E=McAfee;i="6600,9927,10837"; a="383537645" X-IronPort-AV: E=Sophos;i="6.02,157,1688454000"; d="scan'208";a="383537645" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2023 09:58:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10837"; a="992799245" X-IronPort-AV: E=Sophos;i="6.02,157,1688454000"; d="scan'208";a="992799245" Received: from ecochran-mobl1.amr.corp.intel.com (HELO [10.212.244.237]) ([10.212.244.237]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2023 09:58:03 -0700 Message-ID: <789bc8e6-882a-3dfb-7381-fd9b5aca3c77@intel.com> Date: Mon, 18 Sep 2023 09:58:02 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 03/10] platform/x86/intel/ifs: Image loading for new generations Content-Language: en-US To: "Joseph, Jithu" , =?UTF-8?Q?Ilpo_J=c3=a4rvinen?= , "Luck, Tony" Cc: Hans de Goede , "markgross@kernel.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "dave.hansen@linux.intel.com" , "x86@kernel.org" , "hpa@zytor.com" , "rostedt@goodmis.org" , "Raj, Ashok" , LKML , "platform-driver-x86@vger.kernel.org" , "patches@lists.linux.dev" , "Shankar, Ravi V" , "Xu, Pengfei" References: <20230913183348.1349409-1-jithu.joseph@intel.com> <20230913183348.1349409-4-jithu.joseph@intel.com> <10fe57c-c926-9de4-be84-21a0f8abab6d@linux.intel.com> <56b486ce-2a6e-c4c7-8bc5-ceeb7119ba1@linux.intel.com> <826a2b32-bd6a-900a-19fa-e169fcf0d29d@intel.com> From: Dave Hansen In-Reply-To: <826a2b32-bd6a-900a-19fa-e169fcf0d29d@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.3 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Mon, 18 Sep 2023 09:58:50 -0700 (PDT) On 9/18/23 09:51, Joseph, Jithu wrote: > > On 9/18/2023 9:29 AM, Ilpo Järvinen wrote: > >> In this case it is not just about the bitfield itself nor the bit >> allocation order but sharing the storage unit with another member, and to >> further complicate things, members have different alignment requirement >> too (32-bit aligned u8 followed by u32 bitfield). >> > I too verified that the size of the whole structure matches that of MSR 64 bits (8 bytes). > > Initially when IFS scan was added the all MSR structure members were bit-fields, later there was a suggestion to > use basic C types if applicable during subsequent Array BIST patch series. I followed this approach with the current patch series . > > I will change the current series to use all bit-field MSR structures in v2, given mixing basic types and bitfields is a a source of confusion That's the wrong direction. :) What is more obviously correct. This: struct { u16 valid_chunks; u16 total_chunks; u8 error_code; u8 rsvd1; u8 rsvd2; u8 rsvd3; }; or this: struct { u16 valid_chunks; u16 total_chunks; u8 error_code; u32 error_code :8; u32 rsvd :24; }; ?