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Message-ID: <1ea4b72b75f87db5e5ceb0cc88355b44ca2e5884.camel@pengutronix.de>
Subject: Re: [PATCH] arm64: dts: imx8mp: assign parent clock and rate for
 audio clocks
From:   Lucas Stach <l.stach@pengutronix.de>
To:     Shengjiu Wang <shengjiu.wang@gmail.com>
Cc:     marex@denx.de, devicetree@vger.kernel.org, conor+dt@kernel.org,
        kernel@pengutronix.de, alexander.stein@ew.tq-group.com,
        festevam@gmail.com, Shengjiu Wang <shengjiu.wang@nxp.com>,
        Frank.Li@nxp.com, peng.fan@nxp.com, linux-kernel@vger.kernel.org,
        robh+dt@kernel.org, linux-imx@nxp.com,
        krzysztof.kozlowski+dt@linaro.org, aford173@gmail.com,
        shawnguo@kernel.org, s.hauer@pengutronix.de,
        linux-arm-kernel@lists.infradead.org,
        laurent.pinchart@ideasonboard.com
Date:   Tue, 19 Sep 2023 12:22:55 +0200
In-Reply-To: <CAA+D8AM5Lp_vRBVgWXBQ2DFxf1AUG5702rrYrSgvn994GAaFAw@mail.gmail.com>
References: <1695108775-22924-1-git-send-email-shengjiu.wang@nxp.com>
         <8ce3f7e172a747100366ebd14d3bd74fe549ae10.camel@pengutronix.de>
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Am Dienstag, dem 19.09.2023 um 17:59 +0800 schrieb Shengjiu Wang:
> On Tue, Sep 19, 2023 at 4:20 PM Lucas Stach <l.stach@pengutronix.de> wrote:
> > 
> > Hi Shengjiu,
> > 
> > Am Dienstag, dem 19.09.2023 um 15:32 +0800 schrieb Shengjiu Wang:
> > > Assign parent clock for audio AHB and AXI clocks, and assign
> > > clock rate for audio PLL1 and PLL2.
> > > 
> > Please don't do this. Configuring all those clocks in the clock
> > controller is a pain to override if the board uses the PLLs in any
> > other way than the reference design.
> > 
> > The audio AXI and AHB clocks are already properly configured with Adams
> > patch [1], so there is no need for the changes in this patch.
> > 
> > Please set up the audio PLLs in the board DT in peripheral nodes that
> > are actually using those clocks.
> > 
> > Regards,
> > Lucas
> > 
> > [1] https://lore.kernel.org/all/20230819105002.132750-1-aford173@gmail.com/
> 
> For this patch, it changes the AXI clock to 600M.  But the parent clock
> is 800M,  so the result AXI clock is 400M actually, the 800M can't be divided
> to 600MHz.
> 
That's right. Please review that patch and suggest changes if you see a
better option. Adding another conflicting clock setup in the clk
controller node isn't the solution to this.

One possible solution would be to promote the VPU PLL to be the system
PLL running at 600MHz, as there are quite a few peripherals which seem
to need a 600MHz clock for nominal drive mode and we don't need any
other specific VPU clocks, which couldn't be sourced from the system
PLLs + VPU PLL running at 600MHz.

Regards,
Lucas

> Best regards
> Wang shengjiu
> 
> 
> 
> > 
> > > Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> > > ---
> > >  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 16 +++++++++++++---
> > >  1 file changed, 13 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > index 6f2f50e1639c..8a8a2c4aff9f 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > @@ -734,16 +734,26 @@ clk: clock-controller@30380000 {
> > >                                                 <&clk IMX8MP_CLK_A53_CORE>,
> > >                                                 <&clk IMX8MP_CLK_NOC>,
> > >                                                 <&clk IMX8MP_CLK_NOC_IO>,
> > > -                                               <&clk IMX8MP_CLK_GIC>;
> > > +                                               <&clk IMX8MP_CLK_GIC>,
> > > +                                               <&clk IMX8MP_CLK_AUDIO_AHB>,
> > > +                                               <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
> > > +                                               <&clk IMX8MP_AUDIO_PLL1>,
> > > +                                               <&clk IMX8MP_AUDIO_PLL2>;
> > >                               assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
> > >                                                        <&clk IMX8MP_ARM_PLL_OUT>,
> > >                                                        <&clk IMX8MP_SYS_PLL2_1000M>,
> > >                                                        <&clk IMX8MP_SYS_PLL1_800M>,
> > > -                                                      <&clk IMX8MP_SYS_PLL2_500M>;
> > > +                                                      <&clk IMX8MP_SYS_PLL2_500M>,
> > > +                                                      <&clk IMX8MP_SYS_PLL1_800M>,
> > > +                                                      <&clk IMX8MP_SYS_PLL1_800M>;
> > >                               assigned-clock-rates = <0>, <0>,
> > >                                                      <1000000000>,
> > >                                                      <800000000>,
> > > -                                                    <500000000>;
> > > +                                                    <500000000>,
> > > +                                                    <400000000>,
> > > +                                                    <800000000>,
> > > +                                                    <393216000>,
> > > +                                                    <361267200>;
> > >                       };
> > > 
> > >                       src: reset-controller@30390000 {
> > 
>