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From:   Shengjiu Wang <shengjiu.wang@gmail.com>
Date:   Tue, 19 Sep 2023 17:59:48 +0800
Message-ID: <CAA+D8AM5Lp_vRBVgWXBQ2DFxf1AUG5702rrYrSgvn994GAaFAw@mail.gmail.com>
Subject: Re: [PATCH] arm64: dts: imx8mp: assign parent clock and rate for
 audio clocks
To:     Lucas Stach <l.stach@pengutronix.de>
Cc:     Shengjiu Wang <shengjiu.wang@nxp.com>, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de,
        festevam@gmail.com, linux-imx@nxp.com, marex@denx.de,
        peng.fan@nxp.com, alexander.stein@ew.tq-group.com,
        laurent.pinchart@ideasonboard.com, aford173@gmail.com,
        Frank.Li@nxp.com, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
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On Tue, Sep 19, 2023 at 4:20=E2=80=AFPM Lucas Stach <l.stach@pengutronix.de=
> wrote:
>
> Hi Shengjiu,
>
> Am Dienstag, dem 19.09.2023 um 15:32 +0800 schrieb Shengjiu Wang:
> > Assign parent clock for audio AHB and AXI clocks, and assign
> > clock rate for audio PLL1 and PLL2.
> >
> Please don't do this. Configuring all those clocks in the clock
> controller is a pain to override if the board uses the PLLs in any
> other way than the reference design.
>
> The audio AXI and AHB clocks are already properly configured with Adams
> patch [1], so there is no need for the changes in this patch.
>
> Please set up the audio PLLs in the board DT in peripheral nodes that
> are actually using those clocks.
>
> Regards,
> Lucas
>
> [1] https://lore.kernel.org/all/20230819105002.132750-1-aford173@gmail.co=
m/

For this patch, it changes the AXI clock to 600M.  But the parent clock
is 800M,  so the result AXI clock is 400M actually, the 800M can't be divid=
ed
to 600MHz.

Best regards
Wang shengjiu


>
> > Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 16 +++++++++++++---
> >  1 file changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boo=
t/dts/freescale/imx8mp.dtsi
> > index 6f2f50e1639c..8a8a2c4aff9f 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -734,16 +734,26 @@ clk: clock-controller@30380000 {
> >                                                 <&clk IMX8MP_CLK_A53_CO=
RE>,
> >                                                 <&clk IMX8MP_CLK_NOC>,
> >                                                 <&clk IMX8MP_CLK_NOC_IO=
>,
> > -                                               <&clk IMX8MP_CLK_GIC>;
> > +                                               <&clk IMX8MP_CLK_GIC>,
> > +                                               <&clk IMX8MP_CLK_AUDIO_=
AHB>,
> > +                                               <&clk IMX8MP_CLK_AUDIO_=
AXI_SRC>,
> > +                                               <&clk IMX8MP_AUDIO_PLL1=
>,
> > +                                               <&clk IMX8MP_AUDIO_PLL2=
>;
> >                               assigned-clock-parents =3D <&clk IMX8MP_S=
YS_PLL1_800M>,
> >                                                        <&clk IMX8MP_ARM=
_PLL_OUT>,
> >                                                        <&clk IMX8MP_SYS=
_PLL2_1000M>,
> >                                                        <&clk IMX8MP_SYS=
_PLL1_800M>,
> > -                                                      <&clk IMX8MP_SYS=
_PLL2_500M>;
> > +                                                      <&clk IMX8MP_SYS=
_PLL2_500M>,
> > +                                                      <&clk IMX8MP_SYS=
_PLL1_800M>,
> > +                                                      <&clk IMX8MP_SYS=
_PLL1_800M>;
> >                               assigned-clock-rates =3D <0>, <0>,
> >                                                      <1000000000>,
> >                                                      <800000000>,
> > -                                                    <500000000>;
> > +                                                    <500000000>,
> > +                                                    <400000000>,
> > +                                                    <800000000>,
> > +                                                    <393216000>,
> > +                                                    <361267200>;
> >                       };
> >
> >                       src: reset-controller@30390000 {
>