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b=czvWsvfNQdNnIdUecvfyxhrhCcx+4NdiA6M4gyLS7dZVik2xF0FwYILjUgwqUK7/veND+qaqtkfpsn3nFEimSWwHbWsi/1xe5kK89TontYMBExavq69TYOIPqcekcK2/dk1TuKUZzHoe5qsnOlF3/oxKzWzpoRx686nLziQURL/pbSnXGB4imbKtEwhA6p9NY1FiaElVqhqwkFclUgyHilngQWwSOjghtO5a8e8rSjoZKArIMo+rIHaL/5A4cG+ozBSs6xgUHNc7iprki/hEAgOSEoBVQGrrDGYNLZqcVb44fjc4UJmaLqL7ARDYjlIDY3Ux9INgiphnzNr8sDklpA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=kalrayinc.com; Message-ID: Date: Tue, 19 Sep 2023 14:38:22 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v2] i2c: designware: Fix corrupted memory seen in the ISR To: Wolfram Sang , Catalin Marinas , Jan Bottorff , Serge Semin , Yann Sionneau , Will Deacon , Jarkko Nikula , Andy Shevchenko , Mika Westerberg , Jan Dabros , Andi Shyti , Philipp Zabel , linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230913232938.420423-1-janb@os.amperecomputing.com> <37e10c3d-b5ab-75ec-3c96-76e15eb9bef8@sionneau.net> <9de89e14-35bd-415d-97f1-4b6db1258997@os.amperecomputing.com> Content-Language: en-us From: Yann Sionneau In-Reply-To: Content-Type: text/plain; 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Tue, 19 Sep 2023 05:38:49 -0700 (PDT) Hi, On 9/19/23 12:19, Wolfram Sang wrote: >> I also agree that a wmb() in the i2c driver is not the more elegant fix. >> For similar reasons, we hid barriers in the write*() macros, drivers >> need to stay architecture-agnostic as much as possible. > Exactly my thinking. I wanted to read this patch discussion later this > week. But from glimpsing at it so far, I already wondered why there > isn't a memory barrier in the final accessor to the register. The regmap accessors used by the designware driver end up calling writel_relaxed() and readl_relaxed() : https://elixir.bootlin.com/linux/v6.6-rc2/source/drivers/i2c/busses/i2c-designware-common.c#L71 Those usually end up just being volatile accesses, making some kind of compiler barrier preventing the memory mapped register accesses to be moved/removed/merged. I kind of think it's OK. It starts not being OK when you want some ordering between those and some memory accesses in DDR like the problem discussed here. In those cases I would say the smp_* barriers are what we are supposed to use, isn't it? Regards, -- Yann