Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4;
From:   Biju Das <biju.das.jz@bp.renesas.com>
To:     Marc Zyngier <maz@kernel.org>
CC:     Thomas Gleixner <tglx@linutronix.de>,
        Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
        Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Biju Das <biju.das.au@gmail.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-renesas-soc@vger.kernel.org" 
        <linux-renesas-soc@vger.kernel.org>
Subject: RE: [PATCH 3/3] irqchip: renesas-rzg2l: Fix irq storm with edge
 trigger detection for TINT
Thread-Topic: [PATCH 3/3] irqchip: renesas-rzg2l: Fix irq storm with edge
 trigger detection for TINT
Thread-Index: AQHZ6isSnZZc/iqk1kePfAP8iH4mBLAiOWYAgAALsBA=
Date:   Tue, 19 Sep 2023 15:24:53 +0000
Message-ID: <OS0PR01MB5922748F489467BE2539AA1886FAA@OS0PR01MB5922.jpnprd01.prod.outlook.com>
References: <20230918122411.237635-1-biju.das.jz@bp.renesas.com>
        <20230918122411.237635-4-biju.das.jz@bp.renesas.com>
 <86y1h2cjpb.wl-maz@kernel.org>
In-Reply-To: <86y1h2cjpb.wl-maz@kernel.org>
Accept-Language: en-GB, en-US
Content-Language: en-US
x-ms-exchange-antispam-messagedata-chunkcount: 1
x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?1HwhDSQvBbD7yZIPJZ5ZIBdfXnj4pNSn5pF5Q0bl6sIHU1YfWmZuHiMIJueN?=
 =?us-ascii?Q?ZlhaE96IUJ97yfSdYPTSF6SpdA6P+Hwt1357GIHN1ZOZ5MFbf7ObubUXlGjT?=
 =?us-ascii?Q?xPTm3O6WdNb1ioLnPaFTdcvOEsbpSAmU3ZaltqSjO/CsNrMBjDOWd8VG0LlR?=
 =?us-ascii?Q?TE1aghc53v1nllr+6WLhOMBDfIBisQcWuuIG/5uJLQ/5UzQHUhSk4Xx+ckIj?=
 =?us-ascii?Q?lasogruqWNe6j3KZak1cl0wOipbfQIDS8yR6G21pwHxVpANEsl925nbmnnCi?=
 =?us-ascii?Q?7E18gAIRM/DJBeVKxdchyEb6YapgVwmZ8brHBOfP6Ooi6nqExwTldE8nVATB?=
 =?us-ascii?Q?q8rNYm1b1RwD6Ml0JyiE+1RfJpz6dAHGwb69VPwX5yjWuSntNn+xMjRriUSy?=
 =?us-ascii?Q?/nM09P7MIQN1hAoPZhs3AdtwPw2FjIOjFBdUFwWoQ8SdmOIK67lRMg2XL1bP?=
 =?us-ascii?Q?bO8W+RcC5MMUuTkyqi8C1irmuIDqUsfLdvdWqXsv5TczibfMUvl0KPueOy9X?=
 =?us-ascii?Q?sJ8raRAq9IugKQ7T1tkvdWB2peio2G3qESTuGltUnIiXPLxxSEk/yeiMn0mQ?=
 =?us-ascii?Q?Xh9g/OT4uJ0j6lCyBHa/j9S28TSVVbEAfPZUbZdr+yBhn9Ge9HgpKYOo9lvR?=
 =?us-ascii?Q?YaYgpxo0OpZIyoltNxeYxY/w74vzQY2PtJ49CKj157cM+uQ57hjGOXorgqPu?=
 =?us-ascii?Q?N/BaSSLd1PPF0b8uJ+ohybAwo27uErEcvGy3m3+xCkX5fG+mddoKHueh1fHB?=
 =?us-ascii?Q?0rwaJfcB3veU9kpvSZuJkIN7GrrVLFiG9J+919OEI99i7NiF0UBavG8S65Xi?=
 =?us-ascii?Q?obuNoenM/D2a/hSABpjzPEHzc5+0EPYcvEdIQqDW+PX7JrP3vvAbSjC3XGT+?=
 =?us-ascii?Q?8vPd1HgCQW3BY97ybhoEo9lQ1XnBo4uW5vHIOhv9ue70X3Mr0CHDT1dxpuzb?=
 =?us-ascii?Q?jREQlI/N5gpQFUt64MPqKXS237ebU6kwLiOc24f9CoGPgwr084ZIXWOc9nGX?=
 =?us-ascii?Q?cY7NujH13TPHENcSClYHoU3k1Momw6D7nNaMH69EPPC94nbdC9hlm6LdKlFr?=
 =?us-ascii?Q?dZxHLPZUJUdBXzpdYnK6bKz2ol8TAcbeqnvWxgqJp3JuJsHEViU902V1DPuL?=
 =?us-ascii?Q?qnGYlY+/QLPH4XyQYbPQOY9spe0HFVFvjWFQB5PPbpP1sJWDmZkCdItCdZzB?=
 =?us-ascii?Q?TNFhUBjFG5XPDPi0uUsBYlMguGnzoKoOqRAfKUBsyWetFPlOyMfLScx6eg5U?=
 =?us-ascii?Q?9BCbEuuRcf4FUcV2XYuVTTFNgk0g7O8BJOVMhNXCunusUWBBmAqeBOc6hgT0?=
 =?us-ascii?Q?ZSECAv9s/TYyBLGZsJm6SAl6hgbjCKV5SLaD+P3AjLAk4y2ivcaL3F5i6nkq?=
 =?us-ascii?Q?QiY779gqazrTjLew0mHNztycp8hF3iYf9StXBb7CVneQLZ9bKxe+S8MPeudL?=
 =?us-ascii?Q?U2n2i2qvB0SILqq9Mrj5G435NzUN+R0RntFvC8CKHqtptXsnkwdX1sqazd35?=
 =?us-ascii?Q?BjWbkB1WcrzIUA64n5ZVLvy36jBvM/EwaLzM4o5Bj4OZ3Kda2nn9uU1Ts4WQ?=
 =?us-ascii?Q?isclBmym4fskI/J0pOkcLBWF0KMNZ0EzJQ2PAHwsYM7Q/vyjpegzc3tBQ69F?=
 =?us-ascii?Q?gA=3D=3D?=
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-OriginatorOrg: bp.renesas.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-AuthSource: OS0PR01MB5922.jpnprd01.prod.outlook.com
X-MS-Exchange-CrossTenant-Network-Message-Id: e5831a11-e63e-46bb-7f82-08dbb92492ee
X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Sep 2023 15:24:53.7832
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: PgjD2Es93vjGuDFUjv5PxNmbobBgylglj0VCgunQ6vtoNkPMdrxWGQVOsVOXPwMoqoYQEidle9f0M/32FdbRn/o1uPtt9GkpK0BKWbFHv+Y=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYCPR01MB10333
X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,
        SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Tue, 19 Sep 2023 08:25:08 -0700 (PDT)

Hi Marc Zyngier,

Thanks for the feedback.

> Subject: Re: [PATCH 3/3] irqchip: renesas-rzg2l: Fix irq storm with edge
> trigger detection for TINT
>=20
> On Mon, 18 Sep 2023 13:24:11 +0100,
> Biju Das <biju.das.jz@bp.renesas.com> wrote:
> >
> > In case of edge trigger detection, enabling the TINT source causes a
> > phantum interrupt that leads to irq storm. So clear the phantum
> > interrupt in rzg2l_irqc_irq_enable().
> >
> > This issue is observed when the irq handler disables the interrupts
> > using
> > disable_irq_nosync() and scheduling a work queue and in the work
> > queue, re-enabling the interrupt with enable_irq().
> >
> > Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller
> > driver")
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> > ---
> >  drivers/irqchip/irq-renesas-rzg2l.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/irqchip/irq-renesas-rzg2l.c
> > b/drivers/irqchip/irq-renesas-rzg2l.c
> > index 33a22bafedcd..78a9e90512a6 100644
> > --- a/drivers/irqchip/irq-renesas-rzg2l.c
> > +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> > @@ -144,6 +144,12 @@ static void rzg2l_irqc_irq_enable(struct irq_data
> *d)
> >  		reg =3D readl_relaxed(priv->base + TSSR(tssr_index));
> >  		reg |=3D (TIEN | tint) << TSSEL_SHIFT(tssr_offset);
> >  		writel_relaxed(reg, priv->base + TSSR(tssr_index));
> > +		/*
> > +		 * In case of edge trigger detection, enabling the TINT source
> > +		 * cause a phantum interrupt that leads to irq storm. So clear
> > +		 * the phantum interrupt.
> > +		 */
> > +		rzg2l_tint_eoi(d);
>=20
> This looks incredibly unsafe. disable_irq()+enable_irq() with an interrup=
t
> being made pending in the middle, and you've lost that interrupt.

In this driver that will never happen as it clears the TINT source
during disable(), so there won't be any TINT source for interrupt detection=
 after disable().

Cheers,
Biju

> What prevents this scenario?