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Mon, 18 Sep 2023 17:45:36 +0000 Received: from BYAPR11MB3768.namprd11.prod.outlook.com ([fe80::fca6:a86:a250:ad54]) by BYAPR11MB3768.namprd11.prod.outlook.com ([fe80::fca6:a86:a250:ad54%7]) with mapi id 15.20.6792.026; Mon, 18 Sep 2023 17:45:36 +0000 Message-ID: <048e48bb-24da-f23d-50e0-477430d58bac@intel.com> Date: Mon, 18 Sep 2023 10:45:31 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 03/10] platform/x86/intel/ifs: Image loading for new generations Content-Language: en-US To: Dave Hansen , =?UTF-8?Q?Ilpo_J=c3=a4rvinen?= , "Luck, Tony" CC: Hans de Goede , "markgross@kernel.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "dave.hansen@linux.intel.com" , "x86@kernel.org" , "hpa@zytor.com" , "rostedt@goodmis.org" , "Raj, Ashok" , LKML , "platform-driver-x86@vger.kernel.org" , "patches@lists.linux.dev" , "Shankar, Ravi V" , "Xu, Pengfei" References: <20230913183348.1349409-1-jithu.joseph@intel.com> <20230913183348.1349409-4-jithu.joseph@intel.com> <10fe57c-c926-9de4-be84-21a0f8abab6d@linux.intel.com> <56b486ce-2a6e-c4c7-8bc5-ceeb7119ba1@linux.intel.com> <826a2b32-bd6a-900a-19fa-e169fcf0d29d@intel.com> <789bc8e6-882a-3dfb-7381-fd9b5aca3c77@intel.com> From: "Joseph, Jithu" In-Reply-To: <789bc8e6-882a-3dfb-7381-fd9b5aca3c77@intel.com> Content-Type: text/plain; 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Mon, 18 Sep 2023 10:46:49 -0700 (PDT) On 9/18/2023 9:58 AM, Dave Hansen wrote: > On 9/18/23 09:51, Joseph, Jithu wrote: >> >> On 9/18/2023 9:29 AM, Ilpo Järvinen wrote: >> >>> In this case it is not just about the bitfield itself nor the bit >>> allocation order but sharing the storage unit with another member, and to >>> further complicate things, members have different alignment requirement >>> too (32-bit aligned u8 followed by u32 bitfield). >>> >> I too verified that the size of the whole structure matches that of MSR 64 bits (8 bytes). >> >> Initially when IFS scan was added the all MSR structure members were bit-fields, later there was a suggestion to >> use basic C types if applicable during subsequent Array BIST patch series. I followed this approach with the current patch series . >> >> I will change the current series to use all bit-field MSR structures in v2, given mixing basic types and bitfields is a a source of confusion > > That's the wrong direction. :) > > What is more obviously correct. This: > > struct { > u16 valid_chunks; > u16 total_chunks; > u8 error_code; > u8 rsvd1; > u8 rsvd2; > u8 rsvd3; > }; > > or this: > > struct { > u16 valid_chunks; > u16 total_chunks; > u32 error_code :8; > u32 rsvd :24; > }; I will go with the second pattern above, given that pattern can be followed for other MSR structures too, where fields doesn't split as evenly Jithu