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Wed, 20 Sep 2023 05:46:12 +0000 Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38K5kC3N032083 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Sep 2023 05:46:12 GMT Received: from [10.239.132.204] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 19 Sep 2023 22:46:03 -0700 Message-ID: <47d7da41-9d43-4042-b185-709047a1d4b5@quicinc.com> Date: Wed, 20 Sep 2023 13:46:00 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 7/8] arm64: dts: qcom: add uart console support for SM4450 To: Bjorn Andersson CC: , , , , , , , , , , , , , , , , , , , , , , , , , , References: <20230915021509.25773-1-quic_tengfan@quicinc.com> <20230915021509.25773-9-quic_tengfan@quicinc.com> From: Tengfei Fan In-Reply-To: Content-Type: text/plain; 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Tue, 19 Sep 2023 22:47:16 -0700 (PDT) 在 9/20/2023 11:47 AM, Bjorn Andersson 写道: > On Fri, Sep 15, 2023 at 10:15:08AM +0800, Tengfei Fan wrote: >> Add base description of UART, TLMM, interconnect, TCSRCC and SMMU nodes >> which helps SM4450 boot to shell with console on boards with this SoC. >> >> Signed-off-by: Tengfei Fan >> --- >> arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 18 +- >> arch/arm64/boot/dts/qcom/sm4450.dtsi | 313 +++++++++++++++++++++--- >> 2 files changed, 301 insertions(+), 30 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts >> index 00a1c81ca397..0f253a2ba170 100644 >> --- a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts >> +++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts >> @@ -10,9 +10,23 @@ >> model = "Qualcomm Technologies, Inc. SM4450 QRD"; >> compatible = "qcom,sm4450-qrd", "qcom,sm4450"; >> >> - aliases { }; >> + aliases { >> + serial0 = &uart7; >> + }; >> >> chosen { >> - bootargs = "console=hvc0"; >> + stdout-path = "serial0:115200n8"; >> }; >> }; >> + >> +&qupv3_id_0 { >> + status = "okay"; >> +}; >> + >> +&tlmm { >> + gpio-reserved-ranges = <0 4>, <136 1>; >> +}; >> + >> +&uart7 { >> + status = "okay"; >> +}; >> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi > [..] >> + qupv3_id_0: geniqup@ac0000 { >> + compatible = "qcom,geni-se-qup"; >> + reg = <0x0 0x00ac0000 0x0 0x2000>; >> + ranges; >> + clock-names = "m-ahb", "s-ahb"; >> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, >> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; >> + iommus = <&apps_smmu 0x163 0x0>; >> + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; >> + interconnect-names = "qup-core"; > > The patch ends up adding a smorgasbord of different things, some of > which do relate to giving you a console and others mostly not related at > all, because of the iommus and interconnects here. > > If you omit these three properties from this, you can add the > console, then add iommu and interconnect nodes in three clear patches. > > > PS. Commit message says this is all needed for boot-to-shell, but I > don't think you need scm, nor tcsr nodes to achieve that. > > Regards, > Bjorn Hi Bjorn, checked and confirmed your comments, you are right, will remove not related code. -- Thx and BRs, Tengfei Fan