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Wed, 20 Sep 2023 11:24:32 +0000 Received: from IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::d050:882f:a8a7:8263]) by IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::d050:882f:a8a7:8263%4]) with mapi id 15.20.6792.026; Wed, 20 Sep 2023 11:24:32 +0000 From: Inochi Amaoto To: Conor Dooley , Anup Patel Cc: Krzysztof Kozlowski , aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, evicetree@vger.kernel.org, emil.renner.berthing@canonical.com, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, Chen Wang , Inochi Amaoto Subject: Re: [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint Date: Wed, 20 Sep 2023 19:24:21 +0800 Message-ID: X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230920-untimely-untagged-12b75e247afb@wendy> References: <20230920-untimely-untagged-12b75e247afb@wendy> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-TMN: [PGHK3GkX3E2lZkkVf4psTFId/0H1pkdTuOJvwZm9eKg=] X-ClientProxiedBy: SJ0PR03CA0101.namprd03.prod.outlook.com (2603:10b6:a03:333::16) To IA1PR20MB4953.namprd20.prod.outlook.com (2603:10b6:208:3af::19) X-Microsoft-Original-Message-ID: <20230920112421.170713-1-inochiama@outlook.com> MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR20MB4953:EE_|IA1PR20MB6247:EE_ X-MS-Office365-Filtering-Correlation-Id: febcae9d-2131-40a0-ade7-08dbb9cc2955 X-Microsoft-Antispam: BCL:0; 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Wed, 20 Sep 2023 04:24:43 -0700 (PDT) > >Yo, > >On Wed, Sep 20, 2023 at 05:08:41PM +0800, Inochi Amaoto wrote: >>> On Wed, Sep 20, 2023 at 02:39:39PM +0800, Chen Wang wrote: >>>> From: Inochi Amaoto >>>> >>>> Add two new compatible string formatted like `C9xx-clint-xxx` to identify >>>> the timer and ipi device separately, and do not allow c900-clint as the >>>> fallback to avoid conflict. >>>> >>>> Signed-off-by: Inochi Amaoto >>>> Signed-off-by: Chen Wang >>> >>> Have you ignored Krzysztof's comments on this? I don't see a response or >>> a reaction to his comments about the compatibles on the last version. >>> Additionally, where is the user for these? I don't see any drivers that >>> actually make use of these. >>> >> >> Sorry for late reply and wrong message-id. >> >> The clint is parsed by sbi. > >That needs to go in the commit message. Yes, it will. > >> As use the same compatible, the opensbi will >> parse the device twice. This will cause a fault. > >Then only have one compatible with 2 register ranges? Then your SBI >implementation can use those two register ranges to find out the base >address for the mtimer bits and for the mswi bits. >I don't understand why this cannot be done, could you please explain. That is a good idea, but now SBI use the second register ranges as mtimecmp address for aclint. And there is a aclint-mswi in the SBI. Maybe a change is needed? >I also don't see anything in the opensbi repo right now that is using >these (nor could I easily see any patches for opensbi adding this). >Is there another SBI implementation that you are using that I can take >a look at to try and understand this better? > This will be sumbit in a short time. Now we only use it is sophgo vendor SBI, which url is [1]. [1] https://github.com/sophgo/opensbi >>> Why do you need to have 2 compatibles (and therefore 2 devices) for the >>> clint? I thought the clint was a single device, of which the mtimer and >>> mswi bits were just "features"? Having split register ranges isn't a >>> reason to have two compatibles, so I must be missing something here... > >> Sorry for late reply, The clint consists of mtimer and ipi devices, which >> is defined in [1]. > >Yes, I have looked at the spec. I went to check it again before replying >here in case there was something immediately obvious that I was missing. > I think nothing missed. >> This standard shows clint(or the aclint) has two device, > >The wording used here doesn't really matter. It's one interrupt >controller that does mtimer and mswi. > >> but not one. In another word, there is no need to defined mtimer and ipi >> device on the same base address. > >There's also no need to have two compatibles for the same interrupt >controller, so I do not get this reasoning. What actually _requires_ >them to be split? > Yes, it is one, but can be mapped into different address. So I think we need two. >> So we need two compatibles to allow sbi to identify them correctly. > >Why is it not sufficient to identify the individual memory regions? > FYI, Anup. As I have no idea for aclint implementation. >Thanks, >Conor. >