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Date:   Wed, 20 Sep 2023 14:03:01 +0100
From:   Conor Dooley <conor@kernel.org>
To:     Inochi Amaoto <inochiama@outlook.com>
Cc:     Conor Dooley <conor.dooley@microchip.com>,
        Anup Patel <apatel@ventanamicro.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        aou@eecs.berkeley.edu, chao.wei@sophgo.com,
        evicetree@vger.kernel.org, emil.renner.berthing@canonical.com,
        guoren@kernel.org, jszhang@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org,
        linux-riscv@lists.infradead.org, palmer@dabbelt.com,
        paul.walmsley@sifive.com, robh+dt@kernel.org,
        xiaoguang.xing@sophgo.com, Chen Wang <wangchen20@iscas.ac.cn>
Subject: Re: [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint
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On Wed, Sep 20, 2023 at 07:24:21PM +0800, Inochi Amaoto wrote:
> >
> >Yo,
> >
> >On Wed, Sep 20, 2023 at 05:08:41PM +0800, Inochi Amaoto wrote:
> >>> On Wed, Sep 20, 2023 at 02:39:39PM +0800, Chen Wang wrote:
> >>>> From: Inochi Amaoto <inochiama@outlook.com>
> >>>>
> >>>> Add two new compatible string formatted like `C9xx-clint-xxx` to ide=
ntify
> >>>> the timer and ipi device separately, and do not allow c900-clint as =
the
> >>>> fallback to avoid conflict.
> >>>>
> >>>> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> >>>> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> >>>
> >>> Have you ignored Krzysztof's comments on this? I don't see a response=
 or
> >>> a reaction to his comments about the compatibles on the last version.
> >>> Additionally, where is the user for these? I don't see any drivers th=
at
> >>> actually make use of these.
> >>>
> >>
> >> Sorry for late reply and wrong message-id.
> >>
> >> The clint is parsed by sbi.
> >
> >That needs to go in the commit message.
>=20
> Yes, it will.

Thanks.

> >> As use the same compatible, the opensbi will
> >> parse the device twice. This will cause a fault.
> >
> >Then only have one compatible with 2 register ranges? Then your SBI
> >implementation can use those two register ranges to find out the base
> >address for the mtimer bits and for the mswi bits.
> >I don't understand why this cannot be done, could you please explain.
>=20
> That is a good idea, but now SBI use the second register ranges as
> mtimecmp address for aclint. And there is a aclint-mswi in the SBI.
> Maybe a change is needed?

Yeah, I don't think the model for this in OpenSBI at the moment (and
since I checked, in QEMU too) is correct. I think we should re-do things
correctly and it'd be great if things didn't get merged to those
projects that end up being objected to by dt-binding people.
I've started keeping a closer eye on QEMU recently in that regard, but I
am not super attentive. I'll try to be better at that going forward!

>=20
> >I also don't see anything in the opensbi repo right now that is using
> >these (nor could I easily see any patches for opensbi adding this).
> >Is there another SBI implementation that you are using that I can take
> >a look at to try and understand this better?
> >
>=20
> This will be sumbit in a short time.
> Now we only use it is sophgo vendor SBI, which url is [1].
>=20
> [1] https://github.com/sophgo/opensbi

Thanks.

> >>> Why do you need to have 2 compatibles (and therefore 2 devices) for t=
he
> >>> clint? I thought the clint was a single device, of which the mtimer a=
nd
> >>> mswi bits were just "features"? Having split register ranges isn't a
> >>> reason to have two compatibles, so I must be missing something here...
> >
> >> Sorry for late reply, The clint consists of mtimer and ipi devices, wh=
ich
> >> is defined in [1].
> >
> >Yes, I have looked at the spec. I went to check it again before replying
> >here in case there was something immediately obvious that I was missing.
> >
>=20
> I think nothing missed.
>=20
> >> This standard shows clint(or the aclint) has two device,
> >
> >The wording used here doesn't really matter. It's one interrupt
> >controller that does mtimer and mswi.
> >
> >> but not one. In another word, there is no need to defined mtimer and i=
pi
> >> device on the same base address.
> >
> >There's also no need to have two compatibles for the same interrupt
> >controller, so I do not get this reasoning. What actually _requires_
> >them to be split?
> >
>=20
> Yes, it is one, but can be mapped into different address. So I think we
> need two.

Not two compatibles though, just two memory addresses that you need to
locate (or maybe even 3, for SSWI?)

>=20
> >> So we need two compatibles to allow sbi to identify them correctly.
> >
> >Why is it not sufficient to identify the individual memory regions?
> >
>=20
> FYI, Anup. As I have no idea for aclint implementation.
>=20
> >Thanks,
> >Conor.
> >

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