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[209.85.166.49]) by smtp.gmail.com with ESMTPSA id l19-20020a02a893000000b0042b09bde126sm3920828jam.165.2023.09.19.21.48.16 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Sep 2023 21:48:16 -0700 (PDT) Received: by mail-io1-f49.google.com with SMTP id ca18e2360f4ac-7926de0478eso14073139f.0 for ; Tue, 19 Sep 2023 21:48:16 -0700 (PDT) X-Received: by 2002:a5d:9da4:0:b0:79d:2d66:9b3f with SMTP id ay36-20020a5d9da4000000b0079d2d669b3fmr5407772iob.7.1695185296364; Tue, 19 Sep 2023 21:48:16 -0700 (PDT) MIME-Version: 1.0 References: <20230919014439.5795-1-chun-jen.tseng@mediatek.com> <20230919014439.5795-3-chun-jen.tseng@mediatek.com> <0009f224-aac4-6681-fde5-cf1ead94c604@collabora.com> In-Reply-To: From: Fei Shao Date: Wed, 20 Sep 2023 12:47:39 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 2/2] soc: mediatek: svs: add support for mt8188 To: =?UTF-8?B?Q2h1bi1KZW4gVHNlbmcgKOabvuS/iuS7gSk=?= Cc: "matthias.bgg@gmail.com" , "khilman@kernel.org" , =?UTF-8?B?Um9nZXIgTHUgKOmZuOeRnuWCkSk=?= , "angelogioacchino.delregno@collabora.com" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "conor+dt@kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mediatek@lists.infradead.org" , "devicetree@vger.kernel.org" , Project_Global_Chrome_Upstream_Group Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 19 Sep 2023 21:48:46 -0700 (PDT) Hi Mark, On Tue, Sep 19, 2023 at 8:38=E2=80=AFPM Chun-Jen Tseng (=E6=9B=BE=E4=BF=8A= =E4=BB=81) wrote: > > On Tue, 2023-09-19 at 12:52 +0200, AngeloGioacchino Del Regno wrote: > > Il 19/09/23 03:44, Mark Tseng ha scritto: > > > MT8188 svs gpu uses 2-line high bank and low bank to optimize the > > > voltage of opp table for higher and lower frequency respectively. > > > > > > Signed-off-by: Mark Tseng > > > --- > > > + > > > + /* For voltage bin support */ > > > > I already asked you to please send the voltage bin support as a > > separated commit > > because this is for *all SoCs* and not only for 8188. > > > > Again, please separate the voltage bin support from the MT8188 > > support. > > > Hi Angelo, > > I have already checked "voltage bins turn point" with DE, it is support > for *all SoCs* , not only for MT8188. I think Angelo's point is that you should separate this patch into two, whe= re: - "soc: mediatek: svs: Add support for voltage bins" contains changes only related to the "For voltage bin support" part. - "soc: mediatek: svs: Add support for MT8188 SoC" contains code that is specifically for MT8188, i.e. svs_mt8188_efuse_parsing, svs_mt8188_banks etc. It'd be easier for people to review, manage and cherry-pick patches if you add the generic changes apart from the platform-specific code. For example, someone will be able to simply pick up the patch for voltage bin support solely if they are not interested in MT8188. Regards, Fei > > > > soc: mediatek: svs: Add support for voltage bins > > soc: mediatek: svs: Add support for MT8188 SoC > > > > Regards, > > Angelo > >