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Date:   Wed, 20 Sep 2023 15:51:55 +0100
From:   Conor Dooley <conor@kernel.org>
To:     Anup Patel <apatel@ventanamicro.com>
Cc:     Inochi Amaoto <inochiama@outlook.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        aou@eecs.berkeley.edu, chao.wei@sophgo.com,
        evicetree@vger.kernel.org, emil.renner.berthing@canonical.com,
        guoren@kernel.org, jszhang@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org,
        linux-riscv@lists.infradead.org, palmer@dabbelt.com,
        paul.walmsley@sifive.com, robh+dt@kernel.org,
        xiaoguang.xing@sophgo.com, Chen Wang <wangchen20@iscas.ac.cn>,
        Atish Patra <atishp@rivosinc.com>
Subject: Re: [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint
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On Wed, Sep 20, 2023 at 08:08:49PM +0530, Anup Patel wrote:
> On Wed, Sep 20, 2023 at 6:28=E2=80=AFPM Conor Dooley <conor@kernel.org> w=
rote:
> >
> > On Wed, Sep 20, 2023 at 08:40:07PM +0800, Inochi Amaoto wrote:
> > > >On 20/09/2023 14:15, Inochi Amaoto wrote:
> > > >>> On 20/09/2023 08:39, Chen Wang wrote:
> > > >>>> From: Inochi Amaoto <inochiama@outlook.com>
> > > >>>>
> > > >>>> Add two new compatible string formatted like `C9xx-clint-xxx` to=
 identify
> > > >>>> the timer and ipi device separately, and do not allow c900-clint=
 as the
> > > >>>
> > > >>> Why?
> > > >>>
> > > >>
> > > >> If use the same compatible, SBI will process this twice in both ip=
i and
> > > >> timer, use different compatible will allow SBI to treat these as d=
ifferent.
> > > >> AFAIK, the aclint in SBI use the same concepts, which make hard to=
 use the
> > > >> second register range. I have explained in another response.
> > > >
> > > >What is a SBI? Linux driver? If so, why some intermediate Linux driv=
er
> > > >choice should affect bindings?
> > > >Best regards,
> > > >Krzysztof
> > > >
> > >
> > > SBI (Supervisor Binary Interface) is defined by riscv, which is an in=
terface
> > > between the Supervisor Execution Environment (SEE) and the supervisor=
=2E The
> > > detailed documentation can be found in [1].
> > >
> > > The implement of SBI needs fdt info of the platform, which is provide=
d by
> > > kernel. So we need a dt-bindings for these devices, and these will be
> > > processed by SBI.
> > >
> > > [1] https://github.com/riscv-non-isa/riscv-sbi-doc
> >
> > Yeah, this is the unfortunate problem of half-baked bindings (IMO)
> > ending up in OpenSBI (which likely means they also ended up in QEMU).
> > This T-Head stuff is coming across our (metaphorical) desks, so we are
> > obviously going to try to do things correctly. I may end up speaking to
> > Anup later today, if I do I will point him at this thread (if he hasn't
> > seen it already).
>=20
> RISC-V ACLINT is one of those unfortunate non-ISA specs (like
> SiFive PLIC) which is implemented by various organizations but
> not officially ratified by RVI.

Yeah, I brought this stuff up at the weekly pw sync call, and Paul
pointed that out.

> The SiFive CLINT has flexibility related limitations which makes it
> not useful for multi-socket and mult-die systems. The SiFive CLINT
> is also not useful for systems with AIA because with AIA M-mode has
> a new way of doing M-mode IPIs. Due to this reasons, the RISC-V
> ACLINT spec breaks down traditional SiFive CLINT into two separate
> devices namely mtimer and mswi. This allows platforms to implement
> only the required set of devices. The mtimer as defined by the ACLINT
> specifications also allows platforms to place mtime and mtimecmp
> registers at different locations.
>=20
> Refer, https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
>=20
> We need a separate DT bindings document for ACLINT MTIMER
> and ACLINT MSWI because these are separate devices. The
> Sophgo sg2042 SoC should add their implementation specific
> compatible strings in this document.

If the spec isn't frozen, I'm not accepting a binding for the "generic"
version of it. Bindings for this specific implemtnation are okay.
For sure though, squeezing this into the sifive,plic binding isn't
appropriate.

What was pointed out, I think by Samuel, that the reason that this may
need to be split is the fact that there are many possible MTIMER
register ranges & possibly sswi stuff too that would need to be
differentiated.

>=20
> Regards,
> Anup

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Content-Type: application/pgp-signature; name="signature.asc"

-----BEGIN PGP SIGNATURE-----

iHUEARYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZQsHCAAKCRB4tDGHoIJi
0oIxAP4l9Y+OWxR43uIh16s9q+QkJcVDOsWIXdpnb0KYX5AOogD/eVTeoiQKQkzL
Sdw+Zw7PIgPrS0SkTX280B840uhfswE=
=7xPz
-----END PGP SIGNATURE-----

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