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Date:   Wed, 20 Sep 2023 10:53:22 +0100
From:   Conor Dooley <conor.dooley@microchip.com>
To:     Inochi Amaoto <inochiama@outlook.com>
CC:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        <aou@eecs.berkeley.edu>, <chao.wei@sophgo.com>, <conor@kernel.org>,
        <evicetree@vger.kernel.org>, <emil.renner.berthing@canonical.com>,
        <guoren@kernel.org>, <jszhang@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>,
        <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
        <palmer@dabbelt.com>, <paul.walmsley@sifive.com>,
        <robh+dt@kernel.org>, <xiaoguang.xing@sophgo.com>,
        Chen Wang <wangchen20@iscas.ac.cn>
Subject: Re: [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint
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Yo,

On Wed, Sep 20, 2023 at 05:08:41PM +0800, Inochi Amaoto wrote:
> >On Wed, Sep 20, 2023 at 02:39:39PM +0800, Chen Wang wrote:
> >> From: Inochi Amaoto <inochiama@outlook.com>
> >>
> >> Add two new compatible string formatted like `C9xx-clint-xxx` to ident=
ify
> >> the timer and ipi device separately, and do not allow c900-clint as the
> >> fallback to avoid conflict.
> >>
> >> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> >> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
> >
> >Have you ignored Krzysztof's comments on this? I don't see a response or
> >a reaction to his comments about the compatibles on the last version.
> >Additionally, where is the user for these? I don't see any drivers that
> >actually make use of these.
> >
>=20
> Sorry for late reply and wrong message-id.
>=20
> The clint is parsed by sbi.

That needs to go in the commit message.

> As use the same compatible, the opensbi will
> parse the device twice. This will cause a fault.

Then only have one compatible with 2 register ranges? Then your SBI
implementation can use those two register ranges to find out the base
address for the mtimer bits and for the mswi bits.
I don't understand why this cannot be done, could you please explain.
I also don't see anything in the opensbi repo right now that is using
these (nor could I easily see any patches for opensbi adding this).
Is there another SBI implementation that you are using that I can take
a look at to try and understand this better?

> >Why do you need to have 2 compatibles (and therefore 2 devices) for the
> >clint? I thought the clint was a single device, of which the mtimer and
> >mswi bits were just "features"? Having split register ranges isn't a
> >reason to have two compatibles, so I must be missing something here...

> Sorry for late reply, The clint consists of mtimer and ipi devices, which
> is defined in [1].

Yes, I have looked at the spec. I went to check it again before replying
here in case there was something immediately obvious that I was missing.

> This standard shows clint(or the aclint) has two device,

The wording used here doesn't really matter. It's one interrupt
controller that does mtimer and mswi.

> but not one. In another word, there is no need to defined mtimer and ipi
> device on the same base address.

There's also no need to have two compatibles for the same interrupt
controller, so I do not get this reasoning. What actually _requires_
them to be split?

> So we need two compatibles to allow sbi to identify them correctly.

Why is it not sufficient to identify the individual memory regions?

Thanks,
Conor.

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