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From:   Gregory CLEMENT <gregory.clement@bootlin.com>
To:     Chris Packham <chris.packham@alliedtelesis.co.nz>, andrew@lunn.ch,
        sebastian.hesselbarth@gmail.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        kostap@marvell.com
Cc:     linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Chris Packham <chris.packham@alliedtelesis.co.nz>
Subject: Re: [PATCH] ARM64: dts: marvell: cn9310: Use appropriate label for
 spi1 pins
In-Reply-To: <20230820225126.561304-1-chris.packham@alliedtelesis.co.nz>
References: <20230820225126.561304-1-chris.packham@alliedtelesis.co.nz>
Date:   Wed, 20 Sep 2023 11:44:26 +0200
Message-ID: <87h6npfabp.fsf@BL-laptop>
MIME-Version: 1.0
Content-Type: text/plain
Precedence: bulk

Chris Packham <chris.packham@alliedtelesis.co.nz> writes:

> Both the CN9130-CRB and CN9130-DB use the SPI1 interface but had the
> pinctrl node labelled as "cp0_spi0_pins". Use the label "cp0_spi1_pins"
> and update the node name to "cp0-spi-pins-1" to avoid confusion with the
> pinctrl options for SPI0.
>
> Fixes: 4c43a41e5b8c ("arm64: dts: cn913x: add device trees for topology B boards")
> Fixes: 5c0ee54723f3 ("arm64: dts: add support for Marvell cn9130-crb platform")
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
>
> Notes:
>     We noticed this while tracking down a U-Boot bug on one of our
>     platforms. This mislabeling had been copied and we ended up using the
>     label when configuring SPI0 which had the nasty side effect of
>     reconfiguring the NAND/DEV pins into SPI1 mode when SPI0 was probed.
>     
>     It probably went unnoticed because none of the CN9130 platforms
>     supported in upstream U-Boot use NAND.
>
Applied on mvebu/dt64

Thanks,

Gregory

>  arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 4 ++--
>  arch/arm64/boot/dts/marvell/cn9130-db.dtsi  | 4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
> index 32cfb3e2efc3..47d45ff3d6f5 100644
> --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
> +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
> @@ -120,7 +120,7 @@ cp0_sdhci_pins: cp0-sdhi-pins-0 {
>  				       "mpp59", "mpp60", "mpp61";
>  			marvell,function = "sdio";
>  		};
> -		cp0_spi0_pins: cp0-spi-pins-0 {
> +		cp0_spi1_pins: cp0-spi-pins-1 {
>  			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
>  			marvell,function = "spi1";
>  		};
> @@ -170,7 +170,7 @@ &cp0_sdhci0 {
>  
>  &cp0_spi1 {
>  	pinctrl-names = "default";
> -	pinctrl-0 = <&cp0_spi0_pins>;
> +	pinctrl-0 = <&cp0_spi1_pins>;
>  	reg = <0x700680 0x50>,		/* control */
>  	      <0x2000000 0x1000000>;	/* CS0 */
>  	status = "okay";
> diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
> index c7de1ea0d470..6eb6a175de38 100644
> --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
> +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi
> @@ -307,7 +307,7 @@ &cp0_sdhci0 {
>  &cp0_spi1 {
>  	status = "disabled";
>  	pinctrl-names = "default";
> -	pinctrl-0 = <&cp0_spi0_pins>;
> +	pinctrl-0 = <&cp0_spi1_pins>;
>  	reg = <0x700680 0x50>;
>  
>  	flash@0 {
> @@ -371,7 +371,7 @@ cp0_sdhci_pins: cp0-sdhi-pins-0 {
>  				       "mpp59", "mpp60", "mpp61";
>  			marvell,function = "sdio";
>  		};
> -		cp0_spi0_pins: cp0-spi-pins-0 {
> +		cp0_spi1_pins: cp0-spi-pins-1 {
>  			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
>  			marvell,function = "spi1";
>  		};
> -- 
> 2.41.0
>

-- 
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com