Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5;
MIME-Version: 1.0
References: <66b988f0-39fc-2ed3-8f38-151d6a3c9e52@linaro.org>
 <IA1PR20MB49536BFE1254ADEE0E795A26BBF9A@IA1PR20MB4953.namprd20.prod.outlook.com>
 <20230920-8503c6365655d3ef3dadfd53@fedora>
In-Reply-To: <20230920-8503c6365655d3ef3dadfd53@fedora>
From:   Anup Patel <apatel@ventanamicro.com>
Date:   Wed, 20 Sep 2023 20:08:49 +0530
Message-ID: <CAK9=C2WWzc_M49-S+Gi509a6-gk3-89sAZn-ZCRhsQc4JwUpoQ@mail.gmail.com>
Subject: Re: [PATCH v2 06/11] dt-bindings: timer: Add Sophgo sg2042 clint
To:     Conor Dooley <conor@kernel.org>
Cc:     Inochi Amaoto <inochiama@outlook.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        aou@eecs.berkeley.edu, chao.wei@sophgo.com,
        evicetree@vger.kernel.org, emil.renner.berthing@canonical.com,
        guoren@kernel.org, jszhang@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org,
        linux-riscv@lists.infradead.org, palmer@dabbelt.com,
        paul.walmsley@sifive.com, robh+dt@kernel.org,
        xiaoguang.xing@sophgo.com, Chen Wang <wangchen20@iscas.ac.cn>,
        Atish Patra <atishp@rivosinc.com>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Precedence: bulk

On Wed, Sep 20, 2023 at 6:28=E2=80=AFPM Conor Dooley <conor@kernel.org> wro=
te:
>
> On Wed, Sep 20, 2023 at 08:40:07PM +0800, Inochi Amaoto wrote:
> > >On 20/09/2023 14:15, Inochi Amaoto wrote:
> > >>> On 20/09/2023 08:39, Chen Wang wrote:
> > >>>> From: Inochi Amaoto <inochiama@outlook.com>
> > >>>>
> > >>>> Add two new compatible string formatted like `C9xx-clint-xxx` to i=
dentify
> > >>>> the timer and ipi device separately, and do not allow c900-clint a=
s the
> > >>>
> > >>> Why?
> > >>>
> > >>
> > >> If use the same compatible, SBI will process this twice in both ipi =
and
> > >> timer, use different compatible will allow SBI to treat these as dif=
ferent.
> > >> AFAIK, the aclint in SBI use the same concepts, which make hard to u=
se the
> > >> second register range. I have explained in another response.
> > >
> > >What is a SBI? Linux driver? If so, why some intermediate Linux driver
> > >choice should affect bindings?
> > >Best regards,
> > >Krzysztof
> > >
> >
> > SBI (Supervisor Binary Interface) is defined by riscv, which is an inte=
rface
> > between the Supervisor Execution Environment (SEE) and the supervisor. =
The
> > detailed documentation can be found in [1].
> >
> > The implement of SBI needs fdt info of the platform, which is provided =
by
> > kernel. So we need a dt-bindings for these devices, and these will be
> > processed by SBI.
> >
> > [1] https://github.com/riscv-non-isa/riscv-sbi-doc
>
> Yeah, this is the unfortunate problem of half-baked bindings (IMO)
> ending up in OpenSBI (which likely means they also ended up in QEMU).
> This T-Head stuff is coming across our (metaphorical) desks, so we are
> obviously going to try to do things correctly. I may end up speaking to
> Anup later today, if I do I will point him at this thread (if he hasn't
> seen it already).

RISC-V ACLINT is one of those unfortunate non-ISA specs (like
SiFive PLIC) which is implemented by various organizations but
not officially ratified by RVI.

The SiFive CLINT has flexibility related limitations which makes it
not useful for multi-socket and mult-die systems. The SiFive CLINT
is also not useful for systems with AIA because with AIA M-mode has
a new way of doing M-mode IPIs. Due to this reasons, the RISC-V
ACLINT spec breaks down traditional SiFive CLINT into two separate
devices namely mtimer and mswi. This allows platforms to implement
only the required set of devices. The mtimer as defined by the ACLINT
specifications also allows platforms to place mtime and mtimecmp
registers at different locations.

Refer, https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

We need a separate DT bindings document for ACLINT MTIMER
and ACLINT MSWI because these are separate devices. The
Sophgo sg2042 SoC should add their implementation specific
compatible strings in this document.

Regards,
Anup