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[2620:137:e000::3:2]) by mx.google.com with ESMTPS id bw20-20020a056a00409400b0068fcc3406acsi12179167pfb.141.2023.09.20.12.45.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:45:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=lwmL3xER; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id D419C80842E7; Tue, 19 Sep 2023 23:56:44 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233485AbjITG4c (ORCPT + 99 others); Wed, 20 Sep 2023 02:56:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232228AbjITG43 (ORCPT ); Wed, 20 Sep 2023 02:56:29 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8CBDFB9; Tue, 19 Sep 2023 23:56:23 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38K5Xj9E031930; Wed, 20 Sep 2023 06:55:38 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=qcppdkim1; bh=7iPDP/ZoUc8lyMA54RW98h4BCJPDSL9UdqmNcIRYmMA=; b=lwmL3xERJadRy4uf6TQJIhjnknBx68QhEjiqYVW1YQfo2ej0XzQvk06GZTB1zA1iJhfu YPciFcLf+BakjFmBUaZaHLXFI/HCLmt5xApD9SOWOCwSxopzGsgfevTV9hC8vgWklBKP +6uRdrsl61pVszp4zid1Gn1Xw1Jo2JdZcTGqoX4S9PkZqIgPibTxNO1HKqblV8NVANQA qaREgvDB8VsF/9mLYCE70oVc+AkwPsbtb8cuJC/LnfZ2lZ9guJy8Qqb6QkzKTRGklQlN +7ub61XgpXZneXBUaz2VY2N+0XrWPH1DVQDvnxBDVNZDo69jraGsBLR7zOfBDl8SsBXy Tw== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3t78upje40-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Sep 2023 06:55:37 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38K6taLi013223 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Sep 2023 06:55:36 GMT Received: from tengfan2-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Tue, 19 Sep 2023 23:55:28 -0700 From: Tengfei Fan To: , , , , , , , , , CC: , , , , , , , , , , , , , , , , , , Tengfei Fan Subject: [PATCH v3 0/5] soc: qcom: Add uart console support for SM4450 Date: Wed, 20 Sep 2023 14:54:54 +0800 Message-ID: <20230920065459.12738-1-quic_tengfan@quicinc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: tgVgZ3a3OHr-BC95eNaJmTRvobUcRq0x X-Proofpoint-ORIG-GUID: tgVgZ3a3OHr-BC95eNaJmTRvobUcRq0x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-20_02,2023-09-19_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 phishscore=0 mlxscore=0 mlxlogscore=580 suspectscore=0 spamscore=0 clxscore=1015 adultscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309200055 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 19 Sep 2023 23:56:45 -0700 (PDT) This series add base description of UART, TLMM, RPMHCC, GCC and RPMh PD nodes which helps SM4450 boot to shell with console on boards with this SoC. Signed-off-by: Tengfei Fan --- This patch series depends on below patch series: "[PATCH v2 0/4] clk: qcom: Add support for GCC and RPMHCC on SM4450" https://lore.kernel.org/linux-arm-msm/20230909123431.1725728-1-quic_ajipan@quicinc.com/ "[PATCH v3 0/2] pinctl: qcom: Add SM4450 pinctrl driver" https://lore.kernel.org/linux-arm-msm/20230920064739.12562-1-quic_tengfan@quicinc.com/ v2 -> v3: - fix dtbs_check warning - remove interconnect, iommu, scm and tcsr related code - rearrangement dt node - remove smmu, scm and tcsr related documentation update - enable CONFIG_SM_GCC_4450 in defconfig related patch v1 -> v2: - setting "qcom,rpmh-rsc" compatible to the first property - keep order by unit address - move tlmm node into soc node - update arm,smmu.yaml - add enable pinctrl and interconnect defconfig patches - remove blank line - redo dtbs_check check previous discussion here: [1] v2: https://lore.kernel.org/linux-arm-msm/20230915021509.25773-1-quic_tengfan@quicinc.com [2] v2: https://lore.kernel.org/linux-arm-msm/20230908065847.28382-1-quic_tengfan@quicinc.com Ajit Pandey (1): arm64: dts: qcom: sm4450: Add apps_rsc and cmd_db node Tengfei Fan (4): dt-bindings: interrupt-controller: qcom,pdc: document qcom,sm4450-pdc arm64: dts: qcom: sm4450: Add RPMH and Global clock arm64: dts: qcom: add uart console support for SM4450 arm64: defconfig: enable clock controller and pinctrl for SM4450 .../interrupt-controller/qcom,pdc.yaml | 1 + arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 18 ++- arch/arm64/boot/dts/qcom/sm4450.dtsi | 106 ++++++++++++++++++ arch/arm64/configs/defconfig | 2 + 4 files changed, 125 insertions(+), 2 deletions(-) base-commit: dfa449a58323de195773cf928d99db4130702bf7 -- 2.17.1