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Message-ID: <93ff26cc-f9b9-a064-8597-bc1a754d2dc2@linaro.org>
Date:   Wed, 20 Sep 2023 12:03:03 +0200
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Subject: Re: [PATCH v3 4/5] arm64: dts: qcom: add uart console support for
 SM4450
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To:     Tengfei Fan <quic_tengfan@quicinc.com>, agross@kernel.org,
        andersson@kernel.org, tglx@linutronix.de, maz@kernel.org,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org
Cc:     geert+renesas@glider.be, arnd@arndb.de, neil.armstrong@linaro.org,
        nfraprado@collabora.com, rafal@milecki.pl, peng.fan@nxp.com,
        linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        quic_tsoni@quicinc.com, quic_shashim@quicinc.com,
        quic_kaushalk@quicinc.com, quic_tdas@quicinc.com,
        quic_tingweiz@quicinc.com, quic_aiquny@quicinc.com,
        quic_ajipan@quicinc.com, kernel@quicinc.com
References: <20230920065459.12738-1-quic_tengfan@quicinc.com>
 <20230920065459.12738-5-quic_tengfan@quicinc.com>
From:   Konrad Dybcio <konrad.dybcio@linaro.org>
In-Reply-To: <20230920065459.12738-5-quic_tengfan@quicinc.com>
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Precedence: bulk


On 9/20/23 08:54, Tengfei Fan wrote:
> Add base description of UART and TLMM nodes which helps SM4450
> boot to shell with console on boards with this SoC.
> 
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
The SoC change must be separate from the board change.

[...]

Please leave a comment explaining what these GPIOs are
used for.
> +&tlmm {
> +	gpio-reserved-ranges = <0 4>, <136 1>;
> +};

[...]

> +		qupv3_id_0: geniqup@ac0000 {
> +			compatible = "qcom,geni-se-qup";
> +			reg = <0x0 0x00ac0000 0x0 0x2000>;
> +			ranges;
> +			clock-names = "m-ahb", "s-ahb";
> +			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> +				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
property
property-names

[...]

> +
> +			uart7: serial@a88000 {
> +				compatible = "qcom,geni-debug-uart";
> +				reg = <0 0x00a88000 0 0x4000>;
Use 0x0 consistently.

> +				clock-names = "se";
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
property
property-names

> +				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
ditto

[...]

> +			compatible = "qcom,sm4450-tlmm";
> +			reg = <0 0x0f100000 0 0x300000>;
Use 0x0 consistently

> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			gpio-ranges = <&tlmm 0 0 137>;
> +			wakeup-parent = <&pdc>;
> +
> +			qup_uart7_rx: qup-uart7-rx-state {
> +				pins = "gpio23";
> +				function = "qup1_se2_l2";
> +				drive-strength = <2>;
> +				bias-disable;
> +			};
> +
> +			qup_uart7_tx: qup-uart7-tx-state {
> +				pins = "gpio22";
> +				function = "qup1_se2_l2";
> +				drive-strength = <2>;
> +				bias-disable;
> +			};
> +		};
> +
>   		intc: interrupt-controller@17200000 {
>   			compatible = "arm,gic-v3";
>   			reg = <0x0 0x17200000 0x0 0x10000>,     /* GICD */
> @@ -476,7 +525,6 @@
>   				clocks = <&xo_board>;
>   			};
>   		};
> -
Totally unrelated change, fix the patch introducing it instead.

Konrad