Received: by 2002:a05:7412:37c9:b0:e2:908c:2ebd with SMTP id jz9csp2252966rdb; Thu, 21 Sep 2023 13:00:05 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGmzkXfRpK854NANouTIKCkAfaQkulC/HHl7rIc5zj10RjcLbkcb6Dz+IzatlMOKlIqDSO8 X-Received: by 2002:a05:6358:7213:b0:141:162:b0cd with SMTP id h19-20020a056358721300b001410162b0cdmr8785830rwa.19.1695326404780; Thu, 21 Sep 2023 13:00:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695326404; cv=none; d=google.com; s=arc-20160816; b=nZNyV+fMMUB+ZofqbXd9JhITzRxfe9xX1hwJOViLs+ms8AbqWmCZojHbQEAgRixNVF 8b2fC7C+NKNYbYjNzQW96Urcdp7qAQj7JKIOuO7mRobiTWakgogz7klAazJ5IEyJzK8E Ka2pydUdyz2y0RgNEzltPC4Xb67Wz7SEwgVTBtCWwAz3f/teOGF0X8HLjkg2L4JfZH1Y lnQCl2dFRP6xN3NVBj2wrGzebXVYZxgNRi6gBWT8I0paIwR/lhhHPyPuV+TjwfImBr2u C43sJAskkMlOvoUrp1S+HgUeuVJYG2IKXs1PudLDkjjRP3p15Kah+HmQzx5FFYaKGuKC VJyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=LfXllbNXNOrJ5hBJPYWcLPB+5EzqR3sR0rhXVJkM6VM=; fh=pnkcIULy8sAG26d48P4ZzBQZrEneBl46XUCkB8Qn0NQ=; b=NiVJVPerW3d6ooFnxfPn0XANqKqGfKISR3ztTJZ6VeENMzngRTsSzYkTpo/Aake65F WnDFblDtEk1zAsFJUap682XqLft0/7blFRtMMEafbUwbXjbwTbyjLaC8zy7erzT+TofN gn/cvSlpiZTWpSCZCiHRNEyMVJ5HNi2d5H4ls88J4MharTma5NXdnjC1dDaXxE41klZv liFNn1aJhIRBsXBxa8HcrbuBf/mkmzkcpkyCCAvFRNEq+v3ihTOIbYbMrF5MqnQ1H6mh e/FKwn0rtQeKMZPiEdc2Bg/nS2ERo78YOipfLMKSFho+QYWWt2MlVSfU7gKlxM9vtQQH 1cJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Yj43bkTi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from groat.vger.email (groat.vger.email. [23.128.96.35]) by mx.google.com with ESMTPS id q26-20020a631f5a000000b005644a9be955si2064587pgm.179.2023.09.21.13.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 13:00:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Yj43bkTi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 958D08347A6B; Thu, 21 Sep 2023 12:52:12 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229605AbjIUTwH (ORCPT + 99 others); Thu, 21 Sep 2023 15:52:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230451AbjIUTvt (ORCPT ); Thu, 21 Sep 2023 15:51:49 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C0496DE12 for ; Thu, 21 Sep 2023 12:42:30 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 86BC6C433C8; Thu, 21 Sep 2023 19:42:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695325350; bh=KXNNit1NR0Sy8mgpeMe5utffy8Ysa2Z5Lh2pnEXXbtY=; h=From:To:Cc:Subject:Date:From; b=Yj43bkTiD1Tf/7RhNKf5XH2vsSxWTiZ0qB5gqZHiMiih9zRHiHUvlCVdbdGXNkGeH gOOBf3RDuHt6OssPBu4ivRVvQFsocBE9W4b+ELoGb1uKiDRvpzn1EJxGPLCywmNMmG nVckkYw4qU47jbiOIU9O9l5JbY1uDydM04VsTDRcq44TrMis4S7/Vgu0K1btCWd95O AcuBL6+i0IOG7McOEAZmECpK/sZtWeTxhyhXjTDsBrMu0DZ3oVVIEqmVPtoqS7TbEP 1hUFDXvdtDHX5jQ6t3wl4Ve81BQnSzprKy5DsSB8TqNFet1nUZjRoPNEFtVejWb1Qq kkqTrBGaLX0tA== Received: (nullmailer pid 1050671 invoked by uid 1000); Thu, 21 Sep 2023 19:42:28 -0000 From: Rob Herring To: Catalin Marinas , Will Deacon Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] arm64: Add Cortex-A520 CPU part definition Date: Thu, 21 Sep 2023 14:41:51 -0500 Message-Id: <20230921194156.1050055-1-robh@kernel.org> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.4 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75 autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Thu, 21 Sep 2023 12:52:12 -0700 (PDT) Add the CPU Part number for the new Arm design. Cc: stable@vger.kernel.org Signed-off-by: Rob Herring --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 5f6f84837a49..74d00feb62f0 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -79,6 +79,7 @@ #define ARM_CPU_PART_CORTEX_A78AE 0xD42 #define ARM_CPU_PART_CORTEX_X1 0xD44 #define ARM_CPU_PART_CORTEX_A510 0xD46 +#define ARM_CPU_PART_CORTEX_A520 0xD80 #define ARM_CPU_PART_CORTEX_A710 0xD47 #define ARM_CPU_PART_CORTEX_A715 0xD4D #define ARM_CPU_PART_CORTEX_X2 0xD48 @@ -148,6 +149,7 @@ #define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE) #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) +#define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715) #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) -- 2.40.1