Received: by 2002:a05:7412:37c9:b0:e2:908c:2ebd with SMTP id jz9csp2272923rdb; Thu, 21 Sep 2023 13:39:01 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGBS6sBuHVWuLEh4F72CNI8mlFcPr5/0PXn4XD9IZ77K09mOR8h1BxFoeHlhQxbFpoU39qv X-Received: by 2002:a81:9297:0:b0:56d:2d82:63dc with SMTP id j145-20020a819297000000b0056d2d8263dcmr6196550ywg.10.1695328741380; Thu, 21 Sep 2023 13:39:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695328741; cv=none; d=google.com; s=arc-20160816; b=zi1XyHHVLzuuGdEtJtiYt1fcQcgXhSDf7hJmuFbmN+TgLylw7QGrLgha45827/FDRZ 7UtrPNNIcZa15iqoGtN3qKO/ZyeBWB2BSQH7k95PioWS3CL1FLlVPhUZEfewkWWjodBI LRnmYsI9wJlIyeORMOi11RAIBsIdRpWauSmHA8iUTmMfxkt4NjDvevqunGhN5pStwF5g XD5pdhqyZONT2lpBU4Ie0G9IZKXsMMlwqEB9jh8aQs3bgX9qvudl9Img9hxZTIm0/x7P CP6DRX/bu5UZLrUQ+yBjeE5HyP42xp7EukEqiuxm10t94tcR8Q9moXKFplvm12dtPYRq itjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:cc:to:subject :message-id:date:from:in-reply-to:references:mime-version; bh=r4+OkK8Eq1uC527JJWoPUeJIA/9a1YcxTS1XQsYvfDA=; fh=/Zl1W2xIsUDh4Hm8y4wqunf82qFjBEuhBaMw8B9XUyE=; b=vKx8BwxMsbzdRuZU6gX5Duqp0jEHFjaiwCkTcpjaWtol5UjOHblNC8x7YtUbUqtGfv WA1l8MatciZ7IjXF75X+FNCfw2IIeKpOjb5bNzDI1+XmvYzeJSVbsBlTccfTcG0W8lsk qIbTe+t3R9TJYohFkxdkSqXW+ZAaUfAefp9UfrJlLMLdYgg2R9RhmTdUogbx06sGhqDC GnqCMcw7sWZ8sgx9HRY1nxwIQZogZBDIvEkGBM3I9mRCA2bXGB/F7BndH+YDQ9Pj9dc+ XioMts0Ee8PI54zMbTLCt7fj/KTae2SFrrC4czK7UVpVKpCyzAmCbg1zrHQgbZO4jSAN E77A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from morse.vger.email (morse.vger.email. [23.128.96.31]) by mx.google.com with ESMTPS id d19-20020a637353000000b00577f80ddb2esi2093189pgn.705.2023.09.21.13.39.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 13:39:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 79D6980E6099; Thu, 21 Sep 2023 13:22:23 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231193AbjIUUWK convert rfc822-to-8bit (ORCPT + 99 others); Thu, 21 Sep 2023 16:22:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231549AbjIUUVk (ORCPT ); Thu, 21 Sep 2023 16:21:40 -0400 Received: from mail-oi1-x22a.google.com (mail-oi1-x22a.google.com [IPv6:2607:f8b0:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C18164CB08; Thu, 21 Sep 2023 10:14:44 -0700 (PDT) Received: by mail-oi1-x22a.google.com with SMTP id 5614622812f47-3a7f4f7a8easo496670b6e.2; Thu, 21 Sep 2023 10:14:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695316422; x=1695921222; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZKEwqKwPZjLq0SDyfiZ/hvfF1GQ8y1eLifWNF455kwY=; b=B7cFVPIIBVX0cI46+Ze9XhzUcdWBDEILcO/7e9YjFEv1c7gp6iaItqxy2ioWNA/9mq V4lA2q7dJmX0DrgTP+Jr8DF7SbqU6tUIbKr2KD1f88rocjCyA/BBRWomV1ryLEhdlgLP TicgNBJEprIiUn81xHOBu3dQb3NKAU4EfkzibuMpqLLI0lS1iXJb5xQ4Fq8xzWvB9JW/ onG9qZzMF3d0wsJmrXHhwXYBcHj3gXshaRtryTkiec0p0z/qKQ6yQjeTmY0FPhmZSPlz s+QFaoN4RAsmnEbXKiORtbsuUli0zFE54NDoX4sf7dyIR6bOkg8oy5bjz672PkRPjaB4 9G8g== X-Gm-Message-State: AOJu0YwUwwVnyM4CTC7teMLYWA6ZPqS32gnfJ1NCzDebt2zsi2WusnZO HYySenbnPebAiOPMcvD8hAmr2hU9j0Y8jzkq X-Received: by 2002:a25:4603:0:b0:d85:3b6a:c3b8 with SMTP id t3-20020a254603000000b00d853b6ac3b8mr4687097yba.45.1695300686808; Thu, 21 Sep 2023 05:51:26 -0700 (PDT) Received: from mail-yw1-f182.google.com (mail-yw1-f182.google.com. [209.85.128.182]) by smtp.gmail.com with ESMTPSA id x8-20020a259a08000000b00d7b8a1074d4sm301206ybn.57.2023.09.21.05.51.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Sep 2023 05:51:25 -0700 (PDT) Received: by mail-yw1-f182.google.com with SMTP id 00721157ae682-59c0b5f984aso11259777b3.2; Thu, 21 Sep 2023 05:51:25 -0700 (PDT) X-Received: by 2002:a0d:ff05:0:b0:58f:9cd8:9e4d with SMTP id p5-20020a0dff05000000b0058f9cd89e4dmr4594703ywf.46.1695300685164; Thu, 21 Sep 2023 05:51:25 -0700 (PDT) MIME-Version: 1.0 References: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com> <20230912045157.177966-26-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20230912045157.177966-26-claudiu.beznea.uj@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 21 Sep 2023 14:51:11 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 25/37] pinctrl: renesas: rzg2l: adapt function number for RZ/G3S To: Claudiu Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, ulf.hansson@linaro.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com, quic_bjorande@quicinc.com, arnd@arndb.de, konrad.dybcio@linaro.org, neil.armstrong@linaro.org, nfraprado@collabora.com, rafal@milecki.pl, wsa+renesas@sang-engineering.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Thu, 21 Sep 2023 13:22:23 -0700 (PDT) Hi Claudiu, Thanks for your patch! On Tue, Sep 12, 2023 at 6:53 AM Claudiu wrote: > From: Claudiu Beznea > > On RZ/G3S PFC register allow setting 8 functions for individual ports > (function1 to function8). For function1 register need to be configured > with 0, for function8 register need to be configured with 7. > We cannot use zero based addressing when requesting functions from > different code places as documentation (RZG3S_pinfunction_List_r1.0.xlsx) > states explicitly that function0 has different meaning. According to that table, function0 is GPIO. > For this add a new member to struct rzg2l_hwcfg that will keep the > offset that need to be substracted before applying a value to PFC register. > > Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven But one question below... > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -136,9 +136,11 @@ struct rzg2l_register_offsets { > /** > * struct rzg2l_hwcfg - hardware configuration data structure > * @regs: hardware specific register offsets > + * @func_base: base number for port function (see register PFC) > */ > struct rzg2l_hwcfg { > const struct rzg2l_register_offsets regs; > + u8 func_base; > }; > > struct rzg2l_dedicated_configs { > @@ -221,6 +223,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, > unsigned int group_selector) > { > struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); > + const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; > const struct pinctrl_pin_desc *pin_desc; > unsigned int i, *psel_val, *pin_data; > struct function_desc *func; > @@ -247,9 +250,9 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, > off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); > > dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n", port, > - pin, off, psel_val[i]); > + pin, off, psel_val[i] - hwcfg->func_base); > > - rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i]); > + rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base); > } > > return 0; Perhaps the adjustment should be done in rzg2l_dt_subnode_to_map() instead, when obtaining MUX_FUNC() from DT? That would allow you to do some basic validation on it too, which is currently completely missing (reject out-of-range values overflowing into adjacent PFC fields, reject zero on RZ/G3S). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds