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[209.85.128.179]) by smtp.gmail.com with ESMTPSA id s185-20020a8182c2000000b00597e912e67esm309130ywf.131.2023.09.21.05.55.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Sep 2023 05:55:02 -0700 (PDT) Received: by mail-yw1-f179.google.com with SMTP id 00721157ae682-59bd2e19c95so11952697b3.0; Thu, 21 Sep 2023 05:55:02 -0700 (PDT) X-Received: by 2002:a25:a329:0:b0:d84:e73a:6ac9 with SMTP id d38-20020a25a329000000b00d84e73a6ac9mr5019217ybi.24.1695300902378; Thu, 21 Sep 2023 05:55:02 -0700 (PDT) MIME-Version: 1.0 References: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com> <20230912045157.177966-27-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20230912045157.177966-27-claudiu.beznea.uj@bp.renesas.com> From: Geert Uytterhoeven Date: Thu, 21 Sep 2023 14:54:49 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 26/37] pinctrl: renesas: rzg2l: move ds and oi to SoC specific configuration To: Claudiu Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, ulf.hansson@linaro.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com, quic_bjorande@quicinc.com, arnd@arndb.de, konrad.dybcio@linaro.org, neil.armstrong@linaro.org, nfraprado@collabora.com, rafal@milecki.pl, wsa+renesas@sang-engineering.com, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Thu, 21 Sep 2023 14:50:31 -0700 (PDT) Hi Claudiu, On Tue, Sep 12, 2023 at 6:53 AM Claudiu wrote: > From: Claudiu Beznea > > Move drive strength and output impedance values to SoC specific > configuration data structure (struct rzg2l_hwcfg). This allows extending > the drive strength support for RZ/G3S. Along with this the DS values > were converted to uA for simple integration with RZ/G3S support. > > Signed-off-by: Claudiu Beznea Thanks for your patch! Reviewed-by: Geert Uytterhoeven > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -133,13 +133,27 @@ struct rzg2l_register_offsets { > u16 sd_ch; > }; > > +/** > + * enum rzg2l_iolh_index - starting indexes in IOLH specific arrays indices > + * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source > + * @RZG2L_IOLH_IDX_MAX: maximum index > + */ > +enum rzg2l_iolh_index { > + RZG2L_IOLH_IDX_3V3 = 0, > + RZG2L_IOLH_IDX_MAX = 4, > +}; > + > /** > * struct rzg2l_hwcfg - hardware configuration data structure > * @regs: hardware specific register offsets > + * @iolh_groupa_ua: IOLH group A micro amps specific values uA (or µA ;-) > + * @iolh_groupb_oi: IOLH group B output impedance specific values > * @func_base: base number for port function (see register PFC) > */ > struct rzg2l_hwcfg { > const struct rzg2l_register_offsets regs; > + u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX]; > + u16 iolh_groupb_oi[RZG2L_IOLH_IDX_MAX]; > u8 func_base; > }; > > @@ -708,11 +719,11 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, > if (!(cfg & PIN_CFG_IOLH_A)) > return -EINVAL; > > - for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) { > - if (arg == iolh_groupa_mA[index]) > + for (index = RZG2L_IOLH_IDX_3V3; index < RZG2L_IOLH_IDX_3V3 + 4; index++) { I'm not so fond of the hardcoded "+ 4", here and below. Please add and use a #define. > + if (arg == (hwcfg->iolh_groupa_ua[index] / 1000)) > break; > } > - if (index >= ARRAY_SIZE(iolh_groupa_mA)) > + if (index == (RZG2L_IOLH_IDX_3V3 + 4)) > return -EINVAL; > > rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index); Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds