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Fri, 22 Sep 2023 02:36:55 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38M2as3F004876 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Sep 2023 02:36:54 GMT Received: from [10.239.132.204] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 21 Sep 2023 19:36:46 -0700 Message-ID: Date: Fri, 22 Sep 2023 10:36:43 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 4/5] arm64: dts: qcom: add uart console support for SM4450 To: Konrad Dybcio , , , , , , , , , CC: , , , , , , , , , , , , , , , , , References: <20230920065459.12738-1-quic_tengfan@quicinc.com> <20230920065459.12738-5-quic_tengfan@quicinc.com> <93ff26cc-f9b9-a064-8597-bc1a754d2dc2@linaro.org> From: Tengfei Fan In-Reply-To: <93ff26cc-f9b9-a064-8597-bc1a754d2dc2@linaro.org> Content-Type: text/plain; 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Thu, 21 Sep 2023 19:37:55 -0700 (PDT) 在 9/20/2023 6:03 PM, Konrad Dybcio 写道: > > > On 9/20/23 08:54, Tengfei Fan wrote: >> Add base description of UART and TLMM nodes which helps SM4450 >> boot to shell with console on boards with this SoC. >> >> Signed-off-by: Tengfei Fan >> --- > The SoC change must be separate from the board change. > > [...] > > Please leave a comment explaining what these GPIOs are > used for. I checked these gpio setting, the gpio0 ~ gpio3 are for NFC eSE SPI, gpio136 is for LPI Debug. >> +&tlmm { >> +    gpio-reserved-ranges = <0 4>, <136 1>; >> +}; > > [...] > >> +        qupv3_id_0: geniqup@ac0000 { >> +            compatible = "qcom,geni-se-qup"; >> +            reg = <0x0 0x00ac0000 0x0 0x2000>; >> +            ranges; >> +            clock-names = "m-ahb", "s-ahb"; >> +            clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, >> +                 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > property > property-names I will adjust these nodes. > > [...] > >> + >> +            uart7: serial@a88000 { >> +                compatible = "qcom,geni-debug-uart"; >> +                reg = <0 0x00a88000 0 0x4000>; > Use 0x0 consistently. I will update this for using "0x0" instead of "0". > >> +                clock-names = "se"; >> +                clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; > property > property-names I will adjust these nodes. > >> +                interrupts = ; >> +                pinctrl-names = "default"; >> +                pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; > ditto I will adjust these nodes. > > [...] > >> +            compatible = "qcom,sm4450-tlmm"; >> +            reg = <0 0x0f100000 0 0x300000>; > Use 0x0 consistently I will update this for using "0x0" instead of "0" > >> +            interrupts = ; >> +            gpio-controller; >> +            #gpio-cells = <2>; >> +            interrupt-controller; >> +            #interrupt-cells = <2>; >> +            gpio-ranges = <&tlmm 0 0 137>; >> +            wakeup-parent = <&pdc>; >> + >> +            qup_uart7_rx: qup-uart7-rx-state { >> +                pins = "gpio23"; >> +                function = "qup1_se2_l2"; >> +                drive-strength = <2>; >> +                bias-disable; >> +            }; >> + >> +            qup_uart7_tx: qup-uart7-tx-state { >> +                pins = "gpio22"; >> +                function = "qup1_se2_l2"; >> +                drive-strength = <2>; >> +                bias-disable; >> +            }; >> +        }; >> + >>           intc: interrupt-controller@17200000 { >>               compatible = "arm,gic-v3"; >>               reg = <0x0 0x17200000 0x0 0x10000>,     /* GICD */ >> @@ -476,7 +525,6 @@ >>                   clocks = <&xo_board>; >>               }; >>           }; >> - > Totally unrelated change, fix the patch introducing it instead. > > Konrad Hi Konrad, I will remove this rnrelated change. -- Thx and BRs, Tengfei Fan