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From:   Emil Renner Berthing <emil.renner.berthing@canonical.com>
In-Reply-To: <bcdc4623-a37e-455b-8f10-c539e2b04554@codethink.co.uk>
References: <cover.1695189879.git.wangchen20@iscas.ac.cn> <888d57a2d5e62affb8e29e0098402e428facd969.1695189879.git.wangchen20@iscas.ac.cn>
 <bcdc4623-a37e-455b-8f10-c539e2b04554@codethink.co.uk>
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Date:   Fri, 22 Sep 2023 03:40:49 -0700
Message-ID: <CAJM55Z_o7Z8HhaUjrSqjxy1cPjud9Q3GrdqjgFThToxxOCrkgw@mail.gmail.com>
Subject: Re: [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support
To:     Ben Dooks <ben.dooks@codethink.co.uk>,
        Chen Wang <unicornxw@gmail.com>, aou@eecs.berkeley.edu,
        chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org,
        emil.renner.berthing@canonical.com, guoren@kernel.org,
        jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
        palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org,
        xiaoguang.xing@sophgo.com
Cc:     Chen Wang <wangchen20@iscas.ac.cn>
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Ben Dooks wrote:
> On 20/09/2023 07:40, Chen Wang wrote:
> > From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> >
> > Add quirk to skip setting the input clock rate for the uarts on the
> > Sophgo SG2042 SoC similar to the StarFive JH7100.
>
> I'd love an actual explanation of why this is necessary here.

Makes sense. For the JH7100 the commit message is:

  On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to
  exactly 16 * 115200Hz and many other common bitrates. Trying this will
  only result in a higher input clock, but low enough that the UART's
  internal divisor can't come close enough to the baud rate target.
  So rather than try to set the input clock it's better to skip the
  clk_set_rate call and rely solely on the UART's internal divisor.

@Chen Wang is this also true for the SG2042?

/Emil