Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2;
From:   "Li, Xin3" <xin3.li@intel.com>
To:     "Compostella, Jeremy" <jeremy.compostella@intel.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "x86@kernel.org" <x86@kernel.org>
Subject: RE: [PATCH] x86/cpu/intel: Fix MTRR verification for TME enabled
 platforms
Thread-Topic: [PATCH] x86/cpu/intel: Fix MTRR verification for TME enabled
 platforms
Thread-Index: AQHZ7aKWFJxmwKqXn0q3WtdFNO2ey7AoAFcQ
Date:   Sat, 23 Sep 2023 07:37:12 +0000
Message-ID: <SA1PR11MB67344EB62BF798C9FA991552A8FEA@SA1PR11MB6734.namprd11.prod.outlook.com>
References: <87v8c1ua39.fsf@jcompost-mobl.amr.corp.intel.com>
In-Reply-To: <87v8c1ua39.fsf@jcompost-mobl.amr.corp.intel.com>
Accept-Language: en-US
Content-Language: en-US
x-ms-exchange-antispam-messagedata-chunkcount: 1
x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?X8gc0rFOuIaAMXj9NP1ag2eIw4CycYIXR8ixCWEz0i0q8RWfVukvxxUsrFzy?=
 =?us-ascii?Q?AMJNYmXXVx/yE3GasJh2Zrj7MQeai9+vq9LymykuvLM5VL6enUbfywdNxE8W?=
 =?us-ascii?Q?If+twojDl08Jh7nu4Lzyyjcd7Z1SbKTzGYRLLP+EnKPs5hnLXMNSg0gMXf7R?=
 =?us-ascii?Q?KBbZaGrlCpNSESFGkVao6MBRmJxO0YdXLOA2apnXKG4TC9t1uMPe8C1+W9QB?=
 =?us-ascii?Q?wJ4wtoujhvIlisMBhDv2HA9UR/J9sf/8uq8LHBN+ny15Uflq4Oz5A8w7gp6R?=
 =?us-ascii?Q?Gbd6UklEQpA4KbHpJCFjyD9fggS9X5XBT8gOMaiTiim4KC2cIhGm0KaszKAJ?=
 =?us-ascii?Q?4byil3Cwl5X5HZYZgB/wOMOYtxSdENFWJoc8ptAi/d+B/ovzlrUYGTB4/2GE?=
 =?us-ascii?Q?0T52A9c9CkTU0ol4sEhu9JHSXExYLIxup9mUCFNFA2+NA0YBMs1T5gw8CDZt?=
 =?us-ascii?Q?rdA7kLUhiOTII3nUaIdWuZ7LAhf28o36OXgUCE2+cY1DRZXHXOPBDU+8maj6?=
 =?us-ascii?Q?1Xjaq4Zew3mtoIOkPuSLtUFLJO3kUICr16Ea4OK+rU/3MxlYu6yERsswgGqz?=
 =?us-ascii?Q?mDrQ9lL5mUiy6xmcHllUz9YgbaYaNJuSCL1ercJYJx4QtIbJ8XTnEpcrJieT?=
 =?us-ascii?Q?hn0tBJEoJRXcVA+h2Lh67zUnP4/a7oSj9SYOaNJ+UrQTZ5tEVaJlQJpgnoTy?=
 =?us-ascii?Q?Iu098lLoHucu13QTEo5/K6J5bVliqO8RWft3oGweeWyQ32AzWUfYcRr7fWv9?=
 =?us-ascii?Q?tisoGQjEKtvOMCMTuC732m7/SS3KVPyLSVsJJiIn53YSEBVxRKq2AFaGTm7K?=
 =?us-ascii?Q?7TNwPFHtwEwHlX4vMARHnXwUBxazmSWnxrMw3beyj3jmw7DdcoUGj+Yf1DlZ?=
 =?us-ascii?Q?ZFO9vA7qdpyLs5biRoYJs1v8lwGk/zWMPOfQHa0N4GZzOByRxvgAynh45UAH?=
 =?us-ascii?Q?UHloZBPQGZvTDH8U3Ug0V68yRZ0ZipO4f9FTERDmQfRqR2YvG4F9Hcz+VRjP?=
 =?us-ascii?Q?OHrP4tt+wfCWNdriI9I30hD6l9d27e/HZzpRnZXnKh0k5TwWyid57bSz+8kP?=
 =?us-ascii?Q?xj8RY/2OK7xXNyrnu1CkbY9ODw2ZRs68ULEpmaKUSYgQ0g3gKdqavYXAdcSq?=
 =?us-ascii?Q?3t2WROj6VlUS7TMqRKZnY2xAg0Dqc31cd2hVemOJ7cdm0UCPEod4YBG3XsEz?=
 =?us-ascii?Q?cO5y/BrnGGrv8xqXo4ZW1W+ydTaiG2idLj72mYWUMk0TL0kv9FdUt8H3dtax?=
 =?us-ascii?Q?LTEPM9mqYptlkPMQKha2jqyZTN8BXw7Gc1ZzAjy8cTxf2BVeBC008nEOCCd6?=
 =?us-ascii?Q?ZToDQXcFRgJcBD7wP7TtwpyKMN3B/o8iF9hEGGl03LeChiEG99XOS3L3JFvd?=
 =?us-ascii?Q?Gr7VqaGXZ2KgHH/rkIx3f52AhOboS7fZjIgPW5BbrYz1saITSxYajEpwiHhI?=
 =?us-ascii?Q?fFT0VVtTKI6yaA//RZoFNHMOUOMCQ4dDh14KeohJlD2Z5YTAvWxromdlDpAj?=
 =?us-ascii?Q?UqdWT5Iv37V9sKY7v1HX07N2P7yid6wzjvtWn/czjUFzbtO+nW0B74bScu8f?=
 =?us-ascii?Q?5GFrot3pUsibWpBL4k4=3D?=
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-AuthSource: SA1PR11MB6734.namprd11.prod.outlook.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 172daa18-da8c-42c7-73e3-08dbbc07e6b8
X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Sep 2023 07:37:12.4461
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: cg/Zrwkn8ZQY4TWvAv7xsSpuRj8TCmbArmdBPUqr3TCCH67vSEUU0PcaamGyOzg9wCA4dQdl/kwCGPmJ1inHLg==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR11MB7212
X-OriginatorOrg: intel.com
X-Spam-Status: No, score=2.7 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED,
	DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,
	MAILING_LIST_MULTI,RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no
	autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Sat, 23 Sep 2023 00:37:26 -0700 (PDT)
X-Spam-Level: **

Hi Jeremy,

> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index be4045628fd3..34c54432bf00 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -184,6 +184,90 @@ static bool bad_spectre_microcode(struct cpuinfo_x86=
 *c)
>  	return false;
>  }
>=20
> +#define MSR_IA32_TME_ACTIVATE		0x982

I know you're just moving the definitions, however we usually define MSRs
and their bits in arch/x86/include/asm/msr-index.h.

> +
> +/* Helpers to access TME_ACTIVATE MSR */
> +#define TME_ACTIVATE_LOCKED(x)		(x & 0x1)
> +#define TME_ACTIVATE_ENABLED(x)		(x & 0x2)

What about:

#define TME_ACTIVATE_LOCKED(x)		(x & BIT(0))
#define TME_ACTIVATE_ENABLED(x)		(x & BIT(1))

> +
> +#define TME_ACTIVATE_POLICY(x)		((x >> 4) & 0xf)	/* Bits 7:4 */

And:

/* Bits 7:4 are TME activate policy bits */
#define TME_ACTIVATE_POLICY_OFFSET		4
#define TME_ACTIVATE_POLICY_MASK		0xf
#define TME_ACTIVATE_POLICY(x)						\
	((x >> TME_ACTIVATE_POLICY_OFFSET) & TME_ACTIVATE_POLICY_MASK)

> +#define TME_ACTIVATE_KEYID_BITS(x)	((x >> 32) & 0xf)	/* Bits 35:32 */
> +
> +#define TME_ACTIVATE_CRYPTO_ALGS(x)	((x >> 48) & 0xffff)	/* Bits
> 63:48 */

ditto

> @@ -335,6 +419,9 @@ static void early_init_intel(struct cpuinfo_x86 *c)
>  	 */
>  	if (detect_extended_topology_early(c) < 0)
>  		detect_ht_early(c);
> +

Please add a comment here explaining why detect_tme() needs to be called
in early_init_intel().

> +	if (cpu_has(c, X86_FEATURE_TME))
> +		detect_tme(c);
>  }
>=20
>  static void bsp_init_intel(struct cpuinfo_x86 *c)

Thanks!
    Xin